**Vol:** 7 **Issue:** 4

**Published In: October 2017**

**Article No: **4 **Page:** 527-546 doi: 10.13052/jge1904-4720.744

**Hardware Implementation of Three Phase Five-level Inverter with Reduced Number of Switches for PV Based Supply**

T. Porselvi^{1}, K. Deepa^{2} and R. Muthu^{3}

^{1}*Department of Electrical and Electronics Engineering, Sri Sai Ram Engineering College, Sai Leo Nagar, Chennai-44, India*^{2}*Department of Electrical and Electronics Engineering, Amrita School of Engineering, Bengaluru, Amrita Vishwa Vidyapeetham, India*^{3}*Department of Electrical and Electronics Engineering, SSN College of Engineering, Kalavakkam, Chennai, India*

*E-mail: porselvi.eee@sairam.edu.in; deepa.kaliyaperumal@rediffmail.com*

Received 08 December 2017; Accepted 22 March 2018;

Publication 09 April 2018

This paper proposes a three phase five-level inverter which uses a single DC (PV) source, unlike a conventional cascaded H-bridge (CHB) which requires multiple DC (PV) sources, and also a novel Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM) for reduced voltage Total Harmonic Distortion (THD) compared to a conventional SHE-PWM. The proposed inverter uses reduced number of switches when compared to conventional inverter. The proposed three phase inverter is simulated in MATLAB with both conventional and new SHE-PWM techniques. The simulated waveforms of the line, phase voltages and load current are studied in detail. A comparison of THD values is for both conventional and proposed SHE-PWM is presented. This is followed by the hardware implementation of the proposed inverter with the new SHE-PWM, and the results for line, phase voltages and the load currents are again reviewed. The hardware results are found to match the simulation results. The results confirm that the proposed SHE-PWM has the ability to deliver a reduced THD when compared to a conventional SHE-PWM.

- Five-level inverter
- Single DC source
- Conventional Selective Harmonic Elimination
- New Selective Harmonic Elimination
- Total Harmonic Distortion
- Photo-Voltaic (PV)

Multilevel inverters (MLIs) can deliver high voltage with low total harmonic distortion at reduced switching frequency, using low voltage switching devices. Therefore, MLIs have found widespread acceptance in medium and high voltage applications like solar and wind power applications [3, 4, 18–22]. The desired power rating can be achieved without increasing the individual device rating by just increasing or decreasing the number of levels. The more the number of levels, the lower the harmonic content of the output voltage [1, 2]. A m-level inverter produces a phase voltage of m-levels and a line voltage of (2m-1) levels hence; multilevel inverters have the advantage of having less distortion of line voltage.

The common topologies of MLI are Diode Clamped/Neutral Point Clamped (NPC) multilevel inverter, Flying Capacitor (FLC) multilevel inverter and Cascaded H-Bridge (CHB) multilevel inverter. Of these three categories, the CHB inverter is the simplest to design, as they do not require clamping diodes and capacitors. The inverter consists of $\frac{(m-1)}{2}$ isolated DC sources and 2(m-1) IGBT/diode pairs for an m-level inverter. High voltage is achieved by cascading multiple single-phase inverter modules [5]. It offers better flexibility, robustness and is easier to control. The only drawback of the CHB inverter is its requirement of a separate DC source for each H-bridge leading to increased cost [6–8] and it requires 2(m-1) number of switches for m-level. Cascaded inverters with a single DC in which, the circuit uses only one DC source irrespective of number of levels are discussed by the authors in [23] and [24], but the number switches used remain the same as the conventional cascaded inverter. A MLI with a single DC source is proposed with one DC source, but for other stages, capacitors are used which increases the components [25]. Two H-Bridges are connected in series with the second one fed from a capacitor acting as a DC sources instead of DC supply [26]. The paper also proposes a new topology of inverter with single DC source and reduced number of switches and a novel SHE-PWM to achieve a lower THD value.

Section 2 of this paper discusses the proposed five-level CHB inverter with a single DC source. The new SHE-PWM is described in Section 3, simulation and experimental results are dealt in Section 4 and the conclusions is presented in Section 5.

The paper proposes a new inverter topology which removes the necessity of separate DC sources. The inverter uses only one DC source irrespective of number of levels and number of phases. It uses $\frac{(m-1)}{2}$ number of transformers for an m-level inverter. The single phase circuit of the proposed five-level CHB inverter with a single DC source is shown in Figure 1.

This inverter uses only (m-1) switches to implement the m-level inverter and a single DC source. It uses 2 three winding transformers, with two primary windings and one secondary winding. The DC source is connected to the primary side of the transformer through the switches. The secondary windings and the load are connected in series. The switching states to get the five levels of output voltages are given in Table 1.

Output Voltage/Switches | S_{1} |
S_{2} |
S_{11} |
S_{22} |

+V_{DC} |
ON | OFF | OFF | OFF |

+2V_{DC} |
ON | OFF | ON | OFF |

0 | OFF | OFF | OFF | OFF |

–V_{DC} |
OFF | ON | OFF | OFF |

–2V_{DC} |
OFF | ON | OFF | ON |

The various modes of operation are discussed below.

- Mode 1 (S
_{1}-ON): In mode 1 S_{1}is ON, the source current follows the 1^{st}primary winding of the first transformer and the direction of the load current is illustrated in Figure 2. The output voltage is positive and is equal to V_{DC}since the turns ratio is one. - Mode 2 (S
_{1}, S_{11}-ON): In this mode, both S_{1}and S_{11}are ON, the source current flows through the 1^{st}primary windings of both the transformers and the load current is also shown in Figure 3. The output voltage is positive and is equal to 2 V_{DC}. - Mode 3 (S
_{2}-ON): In mode 3 S_{2}is ON, the source current flows through the 2^{nd}primary winding of the first transformer and the direction of the load current is illustrated in Figure 4. The output voltage is negative and is equal to –V_{DC}. - Mode 4 (S
_{2}, S_{22}-ON): In this mode, both S_{2}and S_{22}are ON, the source current flows through the 2^{nd}primary windings of both the transformers and the load current is shown in Figure 5. The output voltage is negative and is equal to –2V_{DC.}

The three phase topology of proposed inverter as shown in Figure 6 requires 3(m-1) numbers of switches while the conventional inverter requires 6(m-1) numbers of switches. Again, the proposed topology uses a single DC source irrespective of number of levels, whereas the conventional three phase inverter requires 3$\frac{(m-1)}{2}$ number of DC sources.

Among the PWM techniques, the multicarrier PWM technique is the most popular. But this technique utilizes a high frequency carrier signal thus increasing switching losses. Hence, ideally a PWM technique at the fundamental frequency is desired. Selective harmonic elimination at fundamental frequency is found to be the best suited PWM technique. This technique has the ability to generate the desired fundamental value by eliminating dominant lower order harmonics [9–11]. It can also determine switching angles by solving a set of non-linear transcendental equations [12–17]. Two transcendental equations are solved to compute two switching angles for a five-level inverter. The Newton-Raphson method, known for its fast iterations, is chosen to solve the two equations using initial approximate values.

Figure 7 illustrates the output voltage waveform of the five-level inverter for a full-cycle. This staircase waveform can be expressed using Fourier series as given by Equation (1).

$${v}_{a}(\omega t)={\displaystyle \sum _{n=1,3,5\dots}^{\infty}\frac{4{V}_{DC}}{n\pi}}\text{\hspace{0.17em}}\left(\mathrm{cos}\text{\hspace{0.17em}}n{\theta}_{1}+\mathrm{cos}n{\theta}_{2}\right)\mathrm{sin}(n\omega t)\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\text{\hspace{0.17em}}\left(1\right)$$Where 𝜃_{1} and 𝜃_{2} represent the switching angles, and 0 < 𝜃_{1} < 𝜃_{2} < π/2. From (1) the fundamental voltage can be expressed as:

The maximum value of the fundamental voltage obtainable is, ${V}_{m1}=\frac{4s{V}_{DC}}{\pi}$, where $s=\frac{(m-1)}{2}$ for a m-level inverter. In order to eliminate the desired harmonic, for example the third harmonic, *n* = 3 is substituted and is equated to zero as in Equation (4). The switching angles for the conventional SHE-PWM (C-SHE-PWM) for a five-level inverter are calculated using the fundamental and the third harmonic Equations (3–4).

Solving the equations using the Newton-Raphson method, the switching angles are at Θ_{1} = 0.1306 radians and Θ_{2} = 0.9166 radians. Hence, the third harmonic is eliminated while the higher order harmonics are retained. Minimization of fifth order harmonic and elimination of third harmonics is done by considering fifth harmonic equation along with the third harmonic equation and ignoring the fundamental one. The fifth harmonic equation equated to a minimum value is given by (5).

Solving Equations (4) and (5), the switching angles for the new SHE-PWM are found to be Θ_{1} = 0.2094 radians and Θ_{2} = 0.8378 radians. When the switches are triggered with these angle values, the voltage THD is found to be lower than that produced with a C-SHE-PWM.

The proposed topology of the single phase five-level inverter is simulated for both C-SHE-PWM and the new SHE-PWM techniques with RL load of 750 Ω, 240 mH. The generated waveforms for output voltage, output current and the FFT analysis are obtained for both. Figure 8 shows the output voltage and output current of the inverter, and Figure 9 shows the THD of the output voltage and current for the C-SHE-PWM. Figure 10(a) show the output voltage and output current of the proposed five-level inverter for the new SHE-PWM with RL load of 750 Ω, 240 mH. The phase angle between voltage and current for the same is theoretically calculated to be 0.3189 msec as illustrated in Figure 10(b). Figure 11 shows the THD of the output voltage and current for the new-SHE-PWM.

From Figure 9 it is observed that fundamental voltage and current are of magnitude 203.4 and 0.2691 respectively, furthermore the 2^{nd}, 3^{rd}, 4^{th} order harmonic in voltage is zero while in current it is 0, 2.5 and 0 respectively for SHE-PWM. The 5^{th} order harmonic of voltage and current is 8 and 7 in magnitude. The illustration in Figure 11(a) depicts that the THD of the new SHE-PWM in 2^{nd}, 3^{rd}, 4^{th}, 5^{th} and 6^{th} order harmonic for voltage is zero, while for current the values are 0, 2.5, 0, 2 and 0 respectively. This clearly proves that 5^{th} voltage order is mitigated in the new SHE, while it is of 8 magnitude in C-SHE-PWM. Similarly in current harmonic it is reduced from a magnitude of 7 to 2.5.

Figures 8 and 11, depicting the simulated waveforms of the phase voltage THDs, it can be deduced that the C-SHE-PWM produced a voltage THD of 20.92% whereas the proposed new SHE-PWM resulted in a phase voltage THD of 17.48% and the line voltage THD is 12.35% (Figure 11(b)). This proves that with the new SHE-PWM, the THD value is lesser when compared to the conventional one.

The three phase circuit of the proposed five-level inverter is also simulated in MATLAB/Simulink with star connected RL load of 750 Ω, 240 mH/phase. The waveforms of the output voltages and currents are shown for the new SHE-PWM.

Figure 12 shows the line and phase voltage waveform of the three phase five-level inverter for the new SHE-PWM. Figure 13 shows the load current of the three phase five-level inverter with new SHE-PWM for the RL-load and its experimental set-up.

The proposed five-level inverter is implemented in hardware with IGBT/Diode pairs. The inverter is switched with the switching angles generated with the new SHE-PWM. The switching patterns are generated in the field programmable gated array (FPGA) board. The FPGA is used to generate 12 PWM signals with 4 PWM signals for each phase. The inverter is experimentally verified with 3-φ RL-load. Figure 14 shows the experimental single phase output voltage and current waveforms for a RL load of 750 Ω, 240 mH/phase. Toroidal transformers with ferrite core are used and hence losses are kept to minimum. Though the size increases, the number of switches used and hence the associated losses are decreased.

Figure 15 shows the experimental waveforms of voltage and current THDs of the proposed MLI for the new SHE-PWM. From the Figures 11(a) and 15 it is realized that the voltage THD of the MLI is 17.48% for simulated output voltage and 17.471% for the experimental output voltage, and hence the new SHE-PWM is found to be satisfactory. From Figures 11(a) and 15, it is also found that the current THD for the RL load obtained in simulation is 12.04%, while the experimental value is 12.116%, which is almost close to the simulated value. Table 2 shows the comparison of voltage THDs for simulated results and experimental results of the proposed inverter.

Figure 16 show the phase and line voltage waveforms for the three-phase five-level inverter for the new SHE-PWM. Figure 17 shows the load current of the three-phase five-level inverter with the new SHE-PWM with RL-load.

Type | Value (%) |

Simulated value of voltage THD with C-SHE-PWM | 20.92 |

Simulated value of voltage THD with new SHE-PWM | 17.48 |

Experimental value of voltage THD with new SHE-PWM | 17.471 |

A new topology of CHB MLI with a single DC and reduced number of switches is proposed to overcome the disadvantage of the conventional CHB inverter. The proposed topology employs a single DC source, irrespective of number of levels and phases. A new SHE-PWM is also proposed which eliminates one more harmonic component, i.e., for a five-level inverter, the C-SHE-PWM eliminates only the 3^{rd} harmonic, but the proposed SHE-PWM eliminates the 5^{th} harmonic also in addition to 3^{rd} harmonic. The simulation is carried out for a single phase inverter with RL-load for both the SHE-PWMs. The voltage, current, voltage THD and current THD are obtained for both the SHE-PWMs. The proposed three phase five-level inverter is also simulated with the new SHE-PWM and the simulated waveforms of phase voltage, line voltage and the line currents are obtained for RL-load. From the waveforms obtained, we can arrive at the conclusion that the new SHE-PWM produces lower THD when compared to that with the C-SHE-PWM. The proposed three phase MLI is also implemented in hardware and verified experimentally with RL-load using the new SHE-PWM. The experimental waveforms of the voltage, current and the THDs are obtained and analyzed. Using the results generated from the proposed CHB inverter with single DC source, we can conclude that using the new SHE-PWM design results in reduced voltage THD.

[1] Nabae, A., Takahashi, I., and Akagi, H. (1981). A new neutral-point-clamped PWM inverter. *IEEE Transactions on Industry Applications*, (5), 518–523.

[2] Bhagwat, P. M., and Stefanovic, V. R. (1983). Generalized structure of a multilevel PWM inverter. *IEEE Transactions on Industry Applications*, (6), 1057–1069.

[3] Ning, J., and He, Y. (2006). Phase-shifted suboptimal pulse-width*1ST IEEE Conference on Industrial Electronics and Applications*, 1–5.

[4] Suh, B. S., Sinha, G., Manjrekar, M. D., and Lipo, T. A. (1998). Multilevel power conversion-an overview of topologies and modulation strategies. *Proceedings of the 6th International Conference Optimization of Electrical and Electronic Equipments*, OPTIM’98, 2, AD-11–AD-24.

[5] Zheng, H., Zhu, B., Zhang, H., and Chen, L. (2010). Carrier Overlaping-switch Frequency optional PWM Method for Cascaded Multilevel Inverter. *International Conference on Electrical and Control Engineering (ICECE)*, 3450–3453.

[6] Song, S. G., Kang, F. S., and Park, S. J. (2009). Cascaded multilevel inverter employing three-phase transformers and single dc input. *IEEE Transactions on Industrial Electronics*, 56(6), 2005–2014.

[7] Porselvi, T., and Muthu, R. (2011). Comparison of cascaded H-Bridge, neutral point clamped and flying capacitor multilevel inverters using multicarrier PWM. *Annual IEEE India Conference (INDICON)*, 1–4.

[8] Prathiba, T., and Renuga, P. (2012). A comparative study of total harmonic distortion in multi level inverter topologies. *Journal of Information Engineering and Applications*, 2(3), 26–36.

[9] Nair, P., and Deepa, K. (2015). Two-port DC-DC converter with flyback inverter for rural lighting applications. *International Conference on Advancements in Power and Energy (TAP Energy)*, 249–253.

[10] Sirisukprasert, S., Lai, J. S., and Liu, T. H. (2002). Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters. *IEEE Transactions on Industrial Electronics,* 49(4), 875–881.

[11] Bouhali, O., Berkouk, E. M., Saudemont, C., and Franois, B. (2004). A five-level diode clamped inverter with self-stabilization of the DC-link voltage for grid connection of distributed generators. *IEEE International Symposium on Industrial Electronics*, 2, 947–952.

[12] Iwaszkiewicz, J., and Perz, J. (2006). Fourier series and wavelet transform applied to stepped waveform synthesis in multilevel convertors. *Proceedings of Electro Technical Institute*, 229, 59–74.

[13] Wang, J., Huang, Y., and Peng, F. Z. (2005). A practical harmonics elimination method for multilevel inverters. *Industry Applications Conference on Fourtieth IAS Annual Meeting*, 3, 1665–1670.

[14] Peng, F. Z., Lai, J. S., McKeever, J. W., and VanCoevering, J. (1996). A multilevel voltage-source inverter with separate DC sources for static var generation. *IEEE Transactions on Industry Applications*, 32(5),

[15] Rodriguez, J., Lai, J. S., and Peng, F. Z. (2002). Multilevel inverters: A survey of topologies, controls, and applications. *IEEE Transactions on Industrial Electronics*, 49(4), 724–738.

[16] Woodford, C., and Phillips, C. (1997). Numerical Methods with Worked Examples, Chapman and Hall, pp. 45–57, First edition: Springer.

[17] Kumar, J., and Das, B. (2008). Selective Harmonic Elimination Technique for a Multilevel Inverter, *Fifteenth National Power Systems Conference (NPSC)*, IIT Bombay, 608–61.

[18] Athira, S., and Deepa, K. (2015). Modified Bidirectional Converter with Current Fed Inverter, *International Journal of Power Electronics and Drive Systems (IJPEDS)*, 6(2), 396–410.

[19] Nair, R., Mahalakshmi, R., and Sindhu Thampatty, K. C., (2015). Performance of three phase 11-level inverter with reduced number of switches using different PWM techniques. *International Conference on Advancements in Power and Energy (TAP Energy)*, 375–380.

[20] Deepa, K., Savitha, P., and Vinodhini, B. (2011). Harmonic analysis of a modified cascaded multilevel inverter. *1st International Conference on Electrical Energy Systems (ICEES)*, 92–97.

[21] Mahalakshmi, R., and Thampatty, K. S. (2015). Implementation of grid connected PV array using quadratic DC-DC converter and single phase multi level inverter. *Indian Journal of Science and Technology*, 8(35).

[22] Deepa, K., Vijayan, A., and Kumar, M. V. (2013). Closed loop controlled solar fed post regulated push-pull converter. *International Conference on Control Communication and Computing (ICCC)*, 409–414.

[23] Porselvi, T., Deepa, K., and Muthu, R. (2018). FPGA Based Selective Harmonic Elimination Technique for Multilevel Inverter. *International Journal of Power Electronics and Drive Systems (IJPEDS)*, 9(1),

[24] Porselvi, T., and Muthu, R. (2012). Seven-level three phase cascaded*ARPN Journal of Engineering and Applied Sciences*, 7(12), 1546–1554.

[25] Khoucha, F., Marouani, K., Benbouzid, M., Kheloui, A., and Mamoune, A. (2013). A 7-Level Single DC source cascaded H-Bridge multilevel inverter with a modified DTC scheme for induction motor-based electric vehicle propulsion. *International Journal of Vehicular Technology*, 1–9.

[26] Iraianbu, P., and Sivakumar, M. (2014). A Single Dc Source Based Cascaded H-Bridge 5-Level Inverter. *International Journal of Innovative Research in Science, Engineering and Technology*, 3(1), 995–1000.

**T. Porselvi**, Associate Professor in the Department of Electrical &

**K. Deepa** graduated from Alagappa chettiar college of engineering and Technology, T.N, India in 1998. She obtained M.Tech degree from Anna University, Guindy campus, T.N, India in 2005. She received Doctoral degree from Jawaharlal Nehru Technological University, Anantapur, A.P, India in 2017. Currently she is working as Assistant professor in Electrical and Electronics Engineering Department, Amrita School of Engineering, Amrita Vishwa Vidyapeetham University, Bangalore, Karnataka, India. She has 19 years of teaching experience. She is a life Member of IETE and ISTE, India and a senior member of IEEE. She has authored 2 textbooks on “Electrical Machines” and “Control Systems”. She has published 18 international journal paper, 2 national journal papers, 27 papers in international conference and 6 papers in national conference. 15 M.Tech Degrees were awarded under her guidance. Her areas of interests include Power electronics, Renewable energy technologies and Control Engineering.

**R. Muthu**, Professor in the Department of Electrical & Electronics

*Journal of Green Engineering, Vol. 7_4*, 527–546.

doi: 10.13052/jge1904-4720.744*This is an Open Access publication.* © 2018 *the Author(s). All rights reserved.*