## Journal of Machine to Machine Communications

Vol: 1    Issue: 3

Published In:   September 2014

### A Differential Cascode Low Noise Amplifier Based on a Positive Feedback Gain Enhancement Technique

Article No: 3    Page: 244-229    doi: 10.13052/jmmc2246-137X.133

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A Differential Cascode Low Noise Amplifier Based on a Positive Feedback Gain Enhancement Technique

Received 1 October 2014; Accepted 7 May 2015; Publication 1 June 2015

Mingcan Cen and Shuxiang Song

• College of Electronic Engineering, Guangxi Normal University, Guilin, China
• Corresponding Author: songshuxiang@mailbox.gxnu.edu.cn

## Abstract

This paper presents a differential low noise amplifier (LNA) based on a new configuration suitable for low-power and low noise applications. By inserting additional positive feedback capacitor connected to drain and source terminal of the cascode transistor, this proposed configuration increases voltage gain because of decreasing the total transconductance by a factor generated a negative conductance. In addition, the differential structure and power-constrained simultaneous noise and input matching (PCSNIM) technique are chosen simultaneously to perform the input matching and to improve the noise figure at the desired band. Using TSMC 0.18μm RF CMOS process, the proposed LNA exhibit a state of the art performance consuming only 7.58mW from a 1.8V power supply. Input and output return loss of the LNA are below than −13dB while achieves a power gain of 18.66dB and a noise figure of 2.03dB at the band of interest.

## Keywords

• low noise amplifier
• gain
• positive feedback
• transconductance

## 1 Introduction

To achieve higher gain and lower noise performance, many kinds of narrow band LNA topologies [24] have been proposed as a way to satisfy this requirement for low power dissipation. In these topologies, typically by improving the structure to increase the linearity, reduce the noise figure or the chip size. Traditional methods usually try to improve the gain of the amplifier by increasing the effective transconductance of the circuit. In contrast to conventional methods, we proposed in this work a positive feedback gain-enhanced technique based on the positive feedback capacitor, as a way to improve the gain of the amplifier. It is shown, by means of feedback capacitor, that the proposed technique decreases the output total transconductance at the drain of the output transistor by generating a negative conductance. Moreover, by this gain-enhanced technique, the gain of the LNA has been increased effectively from 15.76 dB to 18.66 dB without sacrificing bandwidth, linearity, noise and current consumption.

This paper is organized as follows. In Section 2, the description including the PCSNIM technique, the proposed positive feedback gain enhancement technique, the analysis of the stability and the proposed LNA circuit. Section 3 presents the simulation results, discussed and finally compared to those of the recent works. Section 5 concludes the achievements and results.

## 2 Circuit Design and Analysis

### 2.1 LNA Topology with the PCSNIM

Figure 1 shows the typical amplifier circuit using the power-constrained simultaneous noise and input matching (PCSNIM) technique. This well-known technique is usually used to achieve simultaneous input impedance and minimum noise matching, as mentioned in [5]. If the gate resistance and the total parasitic capacitances except the gate-to-source capacitances are neglected, the overall input impedance of this LNA can be expressed as

Figure 1 Conventional cascode LNA.

$Zin=jω(Lg+Ls)+1jω(cgs1+cex)+gm1cgs1+cexLs (1)$

Where Cex, Cgs1 and gm1 are the additional capacitor, the intrinsic gate-to-source capacitor and the transconductance of M1, respectively. Their values are chosen according to PCSNIM technique with corner frequency of 5.8GHz selected in order to achieve a good input reflection coefficient.

The Circuit of equivalent transconductance calculation is shown in Figure 2, to evaluate equivalent transconductance Gm, the following equation can be given

Figure 2 Gm calculation.

$iy=gm1vgs1 (2)$

$vin=jω(Cgs1+Cex)vgs1×(Rs+jωLg)+vgs1 +jωLs[ gm1vgs1+jω(Cgs1+Cex)vgs1 ]n (3)$

then

$Gm(jω)=iyvin(s) =gm11+jω[gm1Ls+Rs(Cgs1+Cex)]−ω2(Cgs1+Cex)(Ls+Lg) (4)$

The equivalent transconductance Gm,eff at resonant frequency is then got by

$Gm,eff=| Gm(jω0) |=gm1Qin=gm12ω0(Cgs1+Cex)Rs (5)$

Where Qin =1/[2RSω0 (Cgs1 + Cex)] is the quality factor of the series resonating input matching circuit.

### 2.2 The Proposed Topology

The LNA with the proposed positive feedback gain-enhanced technique is demonstrated in Figure 3. In this topology, a positive feedback capacitance Cf is inserted between the source and drain terminal of the transistor M2. This phenomenon can be understood by another point of view as the form of oscillator. The capacitors Cgs2, Cf and transistor M2 constitute an oscillator topology with inductive termination at the output. Referring again to Figure 1, the gain of the LNA circuit without the feedback Cf can be expressed as [3]

Figure 3 (a) LNA with the proposed gain enhancement architecture, (b) simplified equivalent circuit of Figure 3 (a).

$Av=gm1QinRload=gm1Qin(1/Gtot)=Gm,eff(1/Gtot) (6)$

Where Gtot is the total transconductance at the drain of M2 and is dominated by the equivalent parallel conductance of the inductor (Gp)

$GP=1/QL12RL1 (7)$

Where RL1 and QL1 are the series resistance and quality factor of inductance L1, respectively. In addition, the LNA gain is proportional to the inductor quality factor and the inductor value as shown below [3]

Where RP is the parallel resistance of L1 obtained from the series to parallel transformation. The above analysis shows that the gain of the circuit can be increased by larger Gm,eff or larger L1.

Assume that ${\omega }_{0}〈〈{g}_{m2}/\left({C}_{gs2}+{C}_{f}\right)$, from the Figure 3 (b), the negative conductance is generated by Cf is

$GN=ω02Cgs2(CN+Cgd2)/gm2 (9)$

So the total transconductance now can be expressed as

$Gtot∧=GP−GN (10)$

The gain of the LNA with a feedback capacitance becomes

$A′v=gm1Qin(1/Gtot∧)=Gm,eff(1/Gtot∧) (11)$

The ${{A}^{\prime }}_{v}$ of the cascode LNA with the proposed technique has the same expression as (6) but with different Gtot as defined by (10). It is observed that the total transconductance from the drain of M2 decrease by times with the increasing feedback, while those from Cf increase. Since no active device is used, this does not increase the power consumption and additional noise. Therefore, the proposed topology provides much higher voltage gain with a help of increased output impedance. The simulation results in Figure 4 and Figure 5 have further confirmed that the voltage gain of the amplifier increases with the increase of capacitor. However, the variation of capacitance will slightly change the matching bandwidth. More important is that large capacitance can deepen feedback degree, for what will degenerate the gain and the stability of the LNA. Furthermore, the choice of Cf must consider the efficiency of stability of the LNA as well as the moderate gain.

Figure 4 Simulated the gain S21 versus frequency with different values of Cf.

Figure 5 Simulated the gain S21 at 5.8GHz with different values of Cf.

### 2.3 Analysis Stability

The stability of the LNA is defined as [3]

$K=1+|Δ|2−|S11|2−|S22|22|S21||S12| (12)$

where |Δ|=S11S22S12S21.

The unconditional stability requirement of LNA is K > 1 and |Δ| < 1 [3]. Compared with the typical LNA topology, the added positive feedback capacitor Cf forms a signal path from the drain of the transistor M2 to the source of M2, which will also increase the instability of the LNA. The limit to amount of feedback is governed by stability consideration. To ensure the unconditional stability, Gtot must be always positive. To further confirm the effect of feedback capacitor and to perform a comparison, the case with different value of feedback capacitor is simulated with the same power dissipation, as shown in Figure 6. From this we can see that large capacitance will weaken the stability of the circuit, so the capacitor selection should take into account the stability.

Figure 6 Cf effect on LNA stability factor Kf.

### 2.4 Proposed LNA Circuit Topology

The proposed gain enhancement LNA topology with positive feedback capacitor is depicted in Figure 7. The differential topology presents a better rejection to common mode interferences unity to some packaging components, a better linearity and gain although it does have its inconveniences, such as a larger consumption and it occupies a larger area. Due to its advantages, we still use this topology. The positive-feedback loop is implemented by adding couple capacitors between the drain and source of the output transistors (M2, M4) and their value should be chosen tradeoff with the gain and stability. The feedback capacitors can increase the chip size, but we will not consider this, because that the gain can be increased at a much higher rate than size. The differential input signals through the transistors M1, M3 will be injected to the source of the transistors, M2 and M4, and these are coupled to the sources of the transistors through capacitors to form feedback path. By this way, the gain will be improved as analysis in Section 2.2.

Figure 7 The schematic of the gain-enhanced differential LNA with positive feedback.

In Figure 7, the input matching network is consisted by Cex and Ls and their size are chosen following the design principle of the PCSNIM technique [5]. The inductors (Lg1, Lg2) are inserted for the input matching to the signal source impedance of 50Ω at the operating frequency (5.8GHz) and therefore their size depends on the input transistor size. When selecting the input transistor’s size, a major design tradeoff is that the current density required for minimum noise figure [12]. In order to obtain the best noise performance, the optimum width of the input transistors (M1, M3) was chosen here according to [12], where the noise figure was optimized under power constrain.

Where ω, L, Cox and Rs are the operating frequency, the length of the input transistors, the gate capacitance per area and the source resistance, respectively. According to [5], once those devices size are determined, the optimum impedance needed to be matched to the optimal noise matching is also determined. The transistors M5, M7 and resistances R1, R3 are served as a current mirror with a reference current as bias circuit. The chosen biasing topology establishes a reference current determined by the value of Rref, while R3 is chosen to be big enough so that the loading effect of the bias circuit on the signal path is negligible. In this circuit, the length of all the transistors are adopted the minimum channel length 0.18um to obtain a higher cutoff frequency. The sizes of the devices on the symmetrical structure have the same parameters. The main component parameters of the LNA are listed as follows: the biased voltage of M1 and M2 are 1.5V, the gate-width of M1 and M2 are 102.6um. Considering the LNA should work at unconditionally stable working condition, the value of feedback capacitance Cf choose 0.025 pF.

## 3 Simulation Results and Discussions

The differential LNA has been designed in TSMC0.18 μm CMOS RF process. Simulations have been performed using Cadence Spectre RF. Using a supply voltage of 1.8V, the designed LNA including the bias circuit draw only 4.21mA resulting in a power consumption of 7.58mW. This is relatively low for a 5.8GHz CMOS differential LNA with a power gain greater than 18.66dB. Figure 8 shows the simulated scattering parameters of the LNA. In the operating frequency of 5.8GHz, a power gain S21 of 18.66dB is achieved. The input return and output return losses (S11, S22) of the LNA are −13.73dB and −14.68dB at 5.8GHz, respectively. The Reverse isolation is −23.01dB; that good reverse isolation is due to utilizing cascode structure.

Figure 8 Simulated S-parameters of the LNA.

To show the effects of the positive feedback capacitor on the frequency response of the gain, the schematic simulation results are illustrated in Figure 9. The obtained results clearly illustrate the important role of the capacitor in improving the gain performance in high frequency. This improvement is obtained by decreasing the total transconductance at the drain of the output transistor by a factor that generated a negative conductance.

Figure 9 Voltage gain simulation results of the LNA with and without Cf.

Figure 10 shows that the proposed LNA achieves a noise figure 2.04dB at the central frequency 5.8GHz, and with a NF ripple of ±0.01dB in the frequency range of 5.725–5.825GHz, which is excellent compared to recently reported designs. Note that, the NF of the LNA coincides with NFmin=1.86dB very well at the frequency of 5.8GHz. Figure 11 shows the simulation result of the input 1-dB compression point (IP1dB). An input sinusoidal signal with a frequency of 5.8GHz is used. The value of IP1dB is about −17.26dBm.

Figure 10 The simulation of noise figure.

Figure 11 The simulation result of the input 1-dB compression point.

Table 1 summarizes the performance of the proposed CMOS differential LNA compared to the recently reported literatures. As can be seen from Table 1, the proposed differential LNA achieves a lower noise figure, a higher voltage gain, and a smaller power dissipation compared to prior techniques listed. These results demonstrate that the proposed technique has an advantage in improving the gain of the LNA circuit, while considering differential topology.

Table 1 Comparison between this work and other reported literatures

## 4 Conclusion

In this paper, a gain enhancement technique using positive feedback for a cascode differential LNA was proposed. Simulation result has shown that, depending on the conventional cascode structure and the proposed design methodology, the gain of the LNA can be significantly improved due to an additional positive feedback capacitor, which decreases the total transconductance at the drain of the output transistor by a factor that generated a negative conductance. Using a 0.18 μm CMOS process, the presented LNA topology consumes only 7.58mW from a 1.8V supply voltage and achieves a power gain of 18.66dB at the operating frequency 5.8GHz. Considering the performance achieved, the proposed techniques is suitable for the implementation of narrowband LNAs in wireless receivers.

## Acknowledgments

This work was supported by the Natural Science Foundation of China (no. 61361011) and the Natural Science Foundation of Guangxi (no. 2014jjAA70058) and was supported by the Project of Outstanding Young Teachers’ Training in Higher Education Institutions of Guangxi (GXQG022014002).

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## Biographies

M. Cen received the B.S. degree in microelectronics from the Guilin University of Electronic Technology, in 2007, Guilin of China. He is currently a teaching assistant at Department of College of Electronic Engineering, Guangxi Normal University, Guilin of China. His research interests include CMOS RF/analog IC design for wireless application.

S. Song received the B.S degree in compute engineering at National University of Defense, Changsha of China and the M.S. degree in microelectronics Guilin Institue of Electronic Technology, Guilin of China and Ph.D. degrees in microelectronics at Huazhong University of Science and Technology, Wuhan of China. He is now a Professor with the College of Electronic Engineering, Guangxi Normal University and a master director of integrated circuit design, VLSI, and Microelectronics at Guangxi Normal University. His research interests include high speed CMOS A/D converters, VLSI technology, LNA design, Analog Integrated Filter Circuits.