Masoud Babaie Delft University of Technology The Netherlands Mina Shahmohammadi Catena The Netherlands Robert Bogdan Staszewski University College Dublin Ireland River Publishers 9788793609495 Series Editors: MASSIMO ALIOTO National University of Singapore Singapore DENNIS SYLVESTER University of Michigan USA KOFI MAKINWA Delft University of Technology The Netherlands Indexing: All books published in this series are submitted to the Web of Science Book Citation Index (BkCI), to SCOPUS, to CrossRef and to Google Scholar for evaluation and indexing. The “River Publishers Series in Circuits & Systems” is a series of comprehensive academic and professional books which focus on theory and applications of Circuit and Systems. This includes analog and digital integrated circuits, memory technologies, system-on-chip and processor design. The series also includes books on electronic design automation and design methodology, as well as computer aided design tools. Books published in the series include research monographs, edited volumes, handbooks and textbooks. The books provide professionals, researchers, educators, and advanced students in the field with an invaluable insight into the latest research and developments. Topics covered in the series include, but are by no means restricted to the following: Analog Integrated Circuits Digital Integrated Circuits Data Converters Processor Architecures System-on-Chip Memory Design Electronic Design Automation For a list of other books in this series, visit www.riverpublishers.com The steady growth of cellular and wireless communications motivates researchers to improve the performance of the systems, overcome the limitations and face new the challenges. One of the key blocks in a wireless radio is the RF oscillator which its purity limits the radio performance. The oscillator’s phase noise in a transmit chain results in power leakage into adjacent channels. In the receive chain, the downconversion of a large interferer with noisy local oscillator (LO) cause reciprocal mixing. Furthermore, in orthogonal frequency-division multiplexing (OFDM) systems, the phase noise leads to inter carrier interference and a degradation in the digital communication bit error rate. The trade-off between oscillator’s phase noise and its power consumption introduce a challenge for oscillator designers. The main focus of this book is on the design and implementation of RF oscillators for wireless (mostly cellular) applications. Each oscillator that is introduced in these chapters tackles an obstacle in RF designs, such as low 1/f2 or low 1/f3 phase noise requirements, low voltage, low power requirements, and wide tuning range requirements. Chapter 1 discusses how a transceiver performance can be limited by an oscillator characteristics. It also reviews how technology scaling affects an oscillator’s performance. Chapter 2 is a reminder how circuit noise up-converts to phase noise in an oscillator, and then briefly introduces and compares different LC oscillator structures. In Chapter 3 we introduce a class-F3 oscillator topology which demonstrates an improved phase noise performance by enforcing a pseudo-square voltage waveform around the LC tank by increasing the third harmonic of the fundamental oscillation voltage through an additional impedance peak. Furthermore, a comprehensive study of circuit-to-phase-noise conversion mechanisms of different classes of RF oscillator is presented. In Chapter 4, we elaborate on a design and implementation of class-F2 oscillators. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second-harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F2 operation. This oscillator specifically addresses the ultra-low phase noise design space while maintaining high power efficiency. Extensive experimental results are also presented at the end of this chapter. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times. This results in an effective impulse sensitivity function (ISF) of a non-zero dc value, which facilitates the flicker (1/f) noise up-conversion into the oscillator’s 1/f3 phase noise. Chapter 5 elaborates a method to reduce a 1/f noise up-conversion in voltage-biased RF oscillators. Chapter 6 introduces and analyzes in detail an oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. This oscillator is specifically addressed IoT application constraints. In Chapter 7 a method to broaden a tuning range of an LC-tank oscillator without sacrificing its area is presented. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. Chapter 8 presents a design guide to estimate the time dependent dielectric beak down of any analog circuit with evaluating life time of class-F oscillators as an example.

Figure 1.1	(a) Evolution of data rates for wireless LAN, cellular, and wireline short links over time; (b) power usage in a smartphone
Figure 1.2	Contribution of RF oscillator to the power consumption of cellular frequency synthesizers and receivers
Figure 1.3	(a) Analog and; (b) digital phase locked loops
Figure 1.4	Oscillator’s open loop and output frequency phase noise
Figure 1.5	Nominal supply voltage versus CMOS technology node for (a) thin-oxide and (b) thick-oxide devices
Figure 1.6	(a) Back-end-of-line (BEOL) metallization; quality factor of (b) a 250 fF capacitor, and (c) a 100 pH inductor in 65 nm and 32 nm CMOS technologies
Figure 1.7	Damascene process steps
Figure 1.8	(a) Thickness variation by erosion in the CMP stage; (b) electromagnetic coupling between the wire and dummy fills; (c) inductor/transformer with lots of dummy metal fills
Figure 1.9	(a) Flicker noise scaling trend; (b) measured excess noise (γ) factor versus drain–source voltage at 10 GHz and Vgs = 1.0 V for different gate lengths of NMOS transistors in 40 nm LP technology
Figure 2.1	A generic RF transceiver
Figure 2.2	Phase response to an impulse current
Figure 2.3	A class-B oscillator (a) schematic; (b) oscillation amplitude versus tail current; (c) ideal and real drain current waveforms; (d) oscillation voltage waveforms
Figure 2.4	The switch capacitor tuning circuit in on and off states
Figure 2.5	(a) A class-C oscillator schematic and (b) its voltage waveforms
Figure 2.6	(a) A class-C with dynamic generation of Vbias; (b) a hybrid class-B/class-C oscillator
Figure 2.7	(a) A class-D oscillator schematic and (b) its voltage waveforms
Figure 3.1	Oscillator schematic: (a) traditional class-B; (b) class-C
Figure 3.2	LC-tank oscillator: (a) noise sources; (b) targeted oscillation voltage (top) and its expected ISF (bottom)
Figure 3.3	Traditional oscillator waveforms in time and frequency domains
Figure 3.4	New oscillator’s waveforms in time and frequency domains
Figure 3.5	The effect of adding third harmonic in the oscillation waveform (top) and its expected ISF (bottom)
Figure 3.6	Transformer-based resonator (a) and its equivalent circuit (b)
Figure 3.7	Ratio of the tank resonant frequencies versus X-factor for different km
Figure 3.8	The transformer-based tank characteristics: (a) the input impedance, Zin magnitude; (b) the trans-impedance, Z21 magnitude; (C) transformer’s secondary to primary voltage gain; (d) the phase of Zin and Z21 (momentum simulation)
Figure 3.9	Typical secondary-to-primary winding voltage gain of the transformer-based resonator versus frequency
Figure 3.10	Two options of the transformer-based class-F3 oscillator: (a) transformer-coupled and (b) cross-coupled. The first option was chosen as more advantageous in this work
Figure 3.11	Root-locus plot of the transformer-based class-F3 oscillator: (a) transformer-coupled structure of Figure 3.10(a); and (b) cross-coupled structure of Figure 3.10(b)
Figure 3.12	(a) Oscillation voltage waveforms and (b) transient response of the class-F3 oscillator
Figure 3.13	Open-loop circuit for unloaded Q-factor calculation (a); its equivalent circuit (b)
Figure 3.14	RF CMOS oscillator noise sources
Figure 3.15	Mechanisms of circuit noise to phase noise conversion in different classes of RF CMOS oscillator
Figure 3.16	Sensitivity of class-F3 oscillator to the position of the second resonant frequency: tank’s input impedance magnitude and phase (top); oscillation waveform (bottom)
Figure 3.17	Die photograph of class-F3 oscillator
Figure 3.18	Measured phase noise at 3.7 GHz and power dissipation of 15 mW. Specifications (MS: mobile station; BTS: basestation) are normalized to the carrier frequency
Figure 3.19	(a) Phase noise and figure of merit (FoM) at 3 MHz offset versus carrier frequency and (b) frequency pushing due to supply voltage variation
Figure 3.20	Measured phase noise at 3.5 GHz and simulated oscillation waveforms: (a) optimum case; (b) exaggerated non-optimum case
Figure 4.1	Phase noise reduction techniques without sacrificing tank’s Q-factor: (a) coupled oscillators, (b) connecting two step-up transformers back-to-back, and (c) its equivalent circuit model
Figure 4.2	Preliminary oscillator schematic and its simulated voltage and estimated current waveforms at f0 = 8 GHz, VDD = 1.2 V, IDC = 33 mA, Leq = 80 pH, and Ceq = 4.95 pF
Figure 4.3	Simulated phase noise performance of the preliminary oscillator of Figure 4.2 versus gate differential oscillation voltage for the ideal and real current sources
Figure 4.4	Drain current of M1,2 devices of Figure 4.2 in time and frequency domains
Figure 4.5	New oscillator’s waveforms in time and frequency domains
Figure 4.6	Effect of adding second harmonic in the oscillation voltage waveform (top) and its expected ISF based on Equation (38) (bottom)
Figure 4.7	Transformer behavior in (a) differential-mode and (b) common-mode excitations
Figure 4.8	New transformer-based resonator: (a) schematic, (b) its simplified equivalent differential-mode circuit (km(DM) ≈ 1), and (c) simplified tank schematic for common-mode input signals (km(CM) ≈ 0)
Figure 4.9	Simulated characteristics of the transformer-based tank of Figure 4.8: (top) magnitude of input impedance Zin; (bottom) tank voltage gain between gate and drain of core devices
Figure 4.10	Transformer-based class-F2 oscillator schematic
Figure 4.11	Simulated oscillation waveforms of the class-F2 oscillator at VDD = 1.2 V and IDC = 29 mA: (top) oscillation voltage of different circuit nodes and (bottom) core transistors drain current
Figure 4.12	Root-locus plot of the class-F2 oscillator
Figure 4.13	Mechanisms of circuit-to-phase-noise conversion across the oscillation period in the class-F2 oscillator: (a) simulated ISF of different tank nodes, (b) equivalent ISF in the simplified oscillator schematic of Figure 4.14, (c) simulated effective power spectral density of the oscillator’s noise sources normalized to KT/Rin, (d) oscillation waveforms and operation region of M1,2, (e) transconductance and channel conductance of M1, (f) loaded Q-factor and effective parallel input resistance of the tank, (g) power spectral density of M1 noise sources normalized to 4KT/Rin, (h) simulated ISF function of M1 channel noise, and (i) simulated effective power spectral density of different noise sources of M1 normalized to KT/Rin
Figure 4.14	Simplified noise source model of the class-F2 oscillator
Figure 4.15	Die photograph of the class-F2 oscillator
Figure 4.16	Measured (blue) and simulated (red) phase noise plots at 4.35 GHz, VDD = 1.3 V and PDC = 41 mW. Specifications (MS: mobile station, BTS: basestation) are normalized to the carrier frequency.
Figure 4.17	Measured phase noise and figure of merit (FoM) at 3 MHz offset versus carrier frequency
Figure 4.18	Measured phase noise at 3 MHz offset frequency from 4.3 GHz carrier versus the oscillator current consumption
Figure 5.1	Class-B oscillator: (a) with tail transistor MT; (b) with tail resistor RT; and their PN when (c) MT is always in saturation; (d) MT enters partially into triode
Figure 5.2	(a) Current harmonic paths; (b) drain current in time and frequency domains; (c) frequency drift due to Groszkowski effect
Figure 5.3	(a) Auxiliary resonances at higher harmonics; (b) current harmonic paths; (c) frequency drift; (d) input impedance of the tank
Figure 5.4	Oscillator example: (a) schematic; (b) VDS, VGS, and gm of M1 transistor when oscillation voltage contains only fundamental component; (c) its ISF, NMF, and effective ISF
Figure 5.5	Conventional tank waveforms: (a) fundamental, VH1, second harmonic, VH2, voltage components, and oscillation waveform, VT2; (b) its ISF, NMF, and effective ISF; (c) Γeff,dc/Γeff,rms for different α2 values
Figure 5.6	Conventional tank waveforms: (a) fundamental, VH1, third harmonic, VH3, voltage component, and oscillation waveform, VT3; (b) its ISF, NMF, and effective ISF
Figure 5.7	Ideal and real current waveforms
Figure 5.8	Tank’s current fundamental and second-harmonic phases in (a) class-D; (b) class-F3; and (c) class-C topologies
Figure 5.9	(a) Voltage-biased class-B oscillator schematics; (b) 1/f3 corner versus IH2/IHn
Figure 5.10	Proposed tank waveforms: (a) fundamental voltage component, VH1; (b) voltage second harmonic in the presence of auxiliary resonance, VH2,aux; (c) oscillation waveform, VT2,aux; (d) its ISF, NMF, and effective ISF
Figure 5.11	(a) VT2,aux for different ϕCM; (b) ϕCM for different QCM when ωCM deviates from 2ω0; (c) Γeff,dc/Γeff,rms for different α2,aux and ϕCM
Figure 5.12	(a) A tank with DM and CM resonances; (b) 1/f3 corner of the oscillator employing this tank; (c) ϕCM; and (d) α2,aux of the tank versus ωCM/ωDM
Figure 5.13	(d) PN and (e) current harmonic components of a class-B oscillator (a), and similar counterparts with noise filtering technique (b) and the proposed method applied (c)
Figure 5.14	A 2-turn “F2” inductor in (a) DM excitation; (b) CM excitation; (c) F2 DM and CM inductances and their ratio; (d) QDM and QCM
Figure 5.15	(a) Inductor-based F2 tank and (b) its input impedance
Figure 5.16	Class-D oscillator: (a) schematic; its (b) waveforms; and (c) gm-transistor ISF, NMF, and effective ISF. Class-D/F2 oscillator: (d) schematic; its (e) waveforms; and (f) gm-transistor ISF, NMF, and effective ISF; (g) their PN performance; and (h) 1/f3 corner sensitivity to ωCM/ωDM
Figure 5.17	Class-D/F2 oscillator: 1/f3 corner over process variation and (b) histogram of PN at 10-kHz offset frequency
Figure 5.18	1:2 transformer when the primary is excited with (a) DM and (b) CM currents
Figure 5.19	(a) Transformer-based F2 tank; (b) its input impedance; (c) DM and CM primary and secondary inductance; (d) primary and secondary inductance quality factor and coupling factor; (e) DM and CM resonant frequencies over TR
Figure 5.20	Class-F3 oscillator: (a) schematic; (b) its waveforms; and (c) gm-transistor ISF, NMF, and effective ISF Class-F2,3 oscillator: (d) schematic; (e) its waveforms; and (f) gm-transistor ISF, NMF, and effective ISF; (g) their PN performance; and (h) 1/f3 corner sensitivity to ωCM/ωDM
Figure 5.21	Class-F2,3 oscillator: 1/f3 corner over process variation and (b) histogram of PN at 10-kHz offset frequency
Figure 5.22	Chip micrographs: (a) class-D/F2 oscillator; (b) class-F2,3 oscillator
Figure 5.23	Class-D/F2 oscillator: measured (a) PN at fmax and fmin; (b) frequency pushing due to supply voltage variation; and (c) 1/f3 corner over tuning range
Figure 5.24	Class-F2,3 oscillator: measured (a) PN at fmax and fmin; (b) frequency pushing due to supply voltage variation; and (c) 1/f3 corner over tuning range
Figure 6.1	BLE system lifetime versus radio current consumption for various battery types
Figure 6.2	Delivered voltage and power density for various harvester types
Figure 6.3	Dependency of various inductor parameters in 28-nm LP CMOS across inductance value: (a) inductor and tank Q-factor; (b) equivalent differential input resistance of the tank; and (c) required tank capacitance at 4.8-GHz resonance. Note that at this point the inductors are without dummy metal fills
Figure 6.4	VDD,min, αI and αV parameters for: (a) cross-coupled NMOS and (b) complementary push-pull oscillators
Figure 6.5	Evolution towards the switching current-source oscillator
Figure 6.6	Various options of a tank providing voltage gain
Figure 6.7	Schematic of the switching current-source oscillator
Figure 6.8	Waveforms and various operational regions of M1–4 transistors across the oscillation period
Figure 6.9	fmax of low-Vt 28 nm transistor versus VDS for different VGS
Figure 6.10	Generic noise circuit model of the disclosed oscillator
Figure 6.11	Simplified schematic of the switching current-source oscillator
Figure 6.12	Simplified schematic of the lower pair of the oscillator
Figure 6.13	Simplified schematic of the upper pair of the oscillator
Figure 6.14	Circuit-to-phase-noise conversion across the oscillation period in the switching current-source oscillator. Simulated (a) channel conductance of M1–4; (b) conductance due to resistive losses; (c) noise factor due to losses; (d) transconductance of M1–4; (e) effective noise factor due to transconductance gain; (f) effective noise factors due to different oscillator’s components
Figure 6.15	Transformer-based tank: (a) schematic; (b) input parallel resistance; (c) voltage gain; and (d) R21 versus ζ-factor
Figure 6.16	(a) Chip micrograph; (b) measured oscillator phase noise and FoM at 3-MHz offset frequency across the tuning range
Figure 6.17	Measured phase noise of this oscillator
Figure 7.1	LC tanks for wide tuning range: (a) resonant mode switching technique; (b) band switching technique; (c) introduced technique
Figure 7.2	(a) Transformer-based tank and (b) its input impedance; (c) capacitively coupled transformer- based tank and (d) its input impedance
Figure 7.3	(a) Simplified schematic of DCO; (b) DCO operates in HB; and (c) LB
Figure 7.4	Differential transconductance schematic
Figure 7.5	(a) Inductance and (b) quality factor of the transformer’s primary and secondary winding. (c) The coupling factor. (d) Chip micrograph
Figure 7.6	PN of the oscillator in the LB
Figure 7.7	PN of the oscillator in the HB
Figure 7.8	Oscillation frequency dependency on supply voltage for different frequency bands
Figure 7.9	(a) A transformer-based tank; (b) limited DM and CM TR due to Cs, c; 1:2 turn transformer: (c) DM excitation; (d) CM excitation; and (e) tank’s input impedance
Figure 7.10	(a) Differential and (b) single-ended capacitor banks
Figure 7.11	Dual core oscillator: (a) schematic; (b) overlap and octave oscillation conditions; and (c) tuning range
Figure 7.12	Dual core oscillator waveforms: (a,b) DM and (c,d) CM
Figure 7.13	Procedures of referring the noise back to the tank from: (a) rds3 and negative conductance; (b) gm of M3; and (c) gm of M4. (d) The equivalent circuit of the Colpitts oscillator
Figure 7.14	Noise sources of the DM oscillator
Figure 7.15	Circuit-to-phase-noise conversion in CM oscillator
Figure 7.16	(a) Drain and source voltage waveforms. (b) gm3: theory and simulations
Figure 7.17	(a–d) Circuit-to-phase-noise conversion in DM oscillator; (e) tail transistor ISF; and (f) PN of CM and DM oscillators at the overlap frequency
Figure 7.18	Transformer characteristics
Figure 7.19	(a) Measured PN at fDM,max, fDM,min; (b) fCM,max and fCM,min. Measured (c) PN and (d) FoM at 10-MHz offset across TR. Frequency pushing due to supply voltage variation in (e) DM and (f) CM oscillators
Figure 7.20	Return current path in the 1:2 transformer
Figure 8.1	Weibull slope versus gate-oxide thickness
Figure 8.2	Comparison of characteristic time-to-breakdown η versus gate voltage in NMOS inversion for different gate-oxide thicknesses from 1.5 to 12 nm. The solid lines represent the result of defect generation model as described. The dashed lines are from the least-square fit using the E-model, as described. The data points (open/solid squares, triangles, and circles) are extracted from literature and scaled to 140°C with an area of 103 μm2
Figure 8.3	Extrapolation steps to the specified condition
Figure 8.4	Class-F oscillator: (a) schematic; (b) waveforms
Figure 8.5	Class-F3 oscillator lifetime estimation due to TDDB for thin- and thick-oxide transistors
Figure 8.6	(a) Measured cumulative failure rate F versus breakdown time TBD for 14 samples of a thick-oxide transistor (176 μm/0.28 μm) at room temperature, (b) the projected η value versus different gate-oxide stress voltage based on the measured ηref, (c) Weibull slope versus gate-oxide thickness extracted from measurement results, and (d) voltage acceleration versus gate-oxide thickness extracted from measurement results
Figure 8.7	Estimated time-to-breakdown (based on the measured parameters of Figure 8.6(a)) of thick-oxide transistors in 65-nm CMOS versus maximum gate-oxide stress voltage for different (a) cumulative failure rates, (b) temperatures, and (c) gate-oxide areas

Table 1.1	Communication standards requirements
Table 3.1	Normalized zero-crossing slope of the novel oscillator
Table 3.2	Comparison of different oscillator’s classes for the same VDD (1.2 V), tank Q-factor (15), RP (i.e. 220 Ω), and carrier frequency (7 GHz) at 3 MHz offset frequency
Table 3.3	Comparison with relevant oscillators
Table 4.1	Comparison between the results of SpectreRF PSS, Pnoise simulation and theoretical equations at 8-GHz carrier for VDD = 1.2 V, Rin = 60 Ω, Leq = 80 pH, γMT = 1.3, and γM1,2 = 1
Table 4.2	Comparison between two flavors of class-F oscillator for the same carrier frequency = 8 GHz, VDD = 1.2 V, tank Q-factor = 14, Δf = 10 MHz, and RP = 240 Ω
Table 4.3	Comparison with relevant ultra-low phase noise oscillators
Table 5.1	Performance summary and comparison with relevant oscillators
Table 6.1	Performance summary of state-of-the-art boost converters
Table 6.2	Minimum PDC for different RF oscillator topologies
Table 6.3	Comparison table of low power oscillators
Table 7.1	Performance summary and comparison with relevant oscillators

4G	Fourth generation
5G	Fifth generation
AM	Amplitude modulation
BEOL	Back-end-of-line
BTS	Base station
BLE	Bluetooth Low Energy
CMP	Chemical-mechanical polishing
CMOS	Complementary metal-oxide-semiconductor
DCO	Digitally controlled oscillator
DT	Direct quantum-mechanical tunneling
FoM	Figure of merit
FinFET	Fin Field-effect transistor
FN	Fowler–Nordheim
GSM	Global system for mobile
ISF	Impulse sensitivity function
IoT	Internet-of-Things
KCL	Kirchhoff’s current law
LTV	Linear time variant
LO	Local oscillator
MoM	Metal-oxide-metal
MOS	Metal-oxide-semiconductor
NBTI	Negative bias temperature instability
OFDM	Orthogonal Frequency-Division Multiplexing
PER	Packet error rate
PLL	Phase lock loop
PM	Phase modulation
PN	Phase noise
PA	Power amplifier
PVT	Process-voltage-temperature
Q-factor	Quality factor
RF	Radio frequency
SNR	Signal-to-noise ratio
SoC	System-on-chips
TDDB	Time-dependent dielectric breakdown
TR	Tuning range
ULP	Ultra-low power
UMTS	Universal mobile telecommunication system
VCO	Voltage control oscillator

1 Introduction	Download As PDF
2 LC Oscillator Structures	Download As PDF
3 A Class-F3 CMOS Oscillator	Download As PDF
4 An Ultra-Low Phase Noise Class-F2 CMOS Oscillator	Download As PDF
5 A 1/f Noise Upconversion Reduction Technique	Download As PDF
6 A Switching Current-Source Oscillator	Download As PDF
7 Tuning Range Extension of an Oscillator Through CM Resonance	Download As PDF
8 A Study of RF Oscillator Reliability in Nanoscale CMOS	Download As PDF

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on RF/mm-wave transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature (PVT) variations. Figure 1.1 (a) illustrates the evolution of data rates for wireless LAN, cellular, and wireline short links over time [1]. Interestingly, there is a constant ∼10× increase in bit rate every five years for both wireline and wireless links. Since mobile terminals inherently operate on batteries, their power budget is basically constant. Hence, an ever-decreasing power per bit is required to maintain the system lifetime. As shown in Figure 1.1 (b), the RF front-end circuitry consumes significant power for typical use cases of mobile terminals such as voice call, web browsing and email [2]. Consequently, power efficiency of RF building blocks has become a major issue, especially when designing system-on-chips (SoC) for wireless communications. On the other hand, in the upcoming years, the wireless Internet-of-Things (IoT) will enable more objects to be sensed and controlled remotely, realizing more integration between the physical and digital worlds. According to communication giant Cisco systems [3] there will be approximately 50 billion Internet-connected objects (things) by 2020, just 2.7 percent of all the things that will be on the planet. However, the system lifetime still tends to be severely limited by its power consumption, available battery technology and efficiency of its energy harvester. Consequently, the key challenge of these wireless sensors is the ability to function at the lowest power possible while being robust to PVT variations. Similarly, the power consumption of RF building blocks should be reduced to satisfy the lifetime demands of IoT systems. Furthermore, RF circuitries such as oscillator and phase lock loop (PLL) should be able to turn on/off quickly to permit high energy-efficiency during intermittent operation. Figure (a) Evolution of data rates for wireless LAN, cellular, and wireline short links over time [1]; (b) power usage in a smartphone [2]. Figure Contribution of RF oscillator to the power consumption of cellular frequency synthesizers and receivers. The RF oscillator is the second most power hungry block of a wireless radio (after power amplifiers). As shown in Figure 1.2, the RF oscillator consumes a disproportionate amounts of the power of a cellular frequency synthesizer [4, 5] and burns more than 30% of the cellular receiver power [6, 7]. Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. For IoT applications, the commercial perspective is now focusing on Bluetooth Low Energy (BLE). In the state-of-the-art BLE radios [8–10], the PLL power consumption is merely 3–4× lower than that of power amplifier (PA) at the maximum BLE output power of 1 mW. However, the frequency synthesizer activity is much longer than that of a PA, making the PLL the most energy-hungry block in a BLE transceiver. Consequently, RF oscillators, as one of the BLE transceiver’s most power hungry circuitry, must be very power efficient. On the other hand the RF oscillators’ purity limits the transceiver performance. The oscillator’s phase noise in a transmit chain results in power leakage into adjacent channels. In the receive chain, the down-conversion of a large interferer with a noisy local oscillator (LO) causes reciprocal mixing. Furthermore, in orthogonal frequency-division multiplexing (OFDM) systems, the phase noise leads to inter-carrier interference and a degradation in the digital communication bit error rate. Table 1.1 summarizes the frequency bands and the phase noise requirement specifications for some communication standards. The trade-offs between oscillator’s phase noise and its power consumption introduce a challenge for oscillator designers. To achieve high frequency accuracy, oscillators are incorporated in a PLL (as is shown in Figure 1.3 for both analog and digital PLLs), they can benefit from high pass nature of filtering of their noise by the loop (see Figure 1.4). This reduction of the oscillator’s low frequency noise in the synthesizer is highly dependent on the loop bandwidth. The loop bandwidth of the PLL is usually chosen to minimize the noise contribution of the frequency reference and charge pumps. However, if this bandwidth is less than the 1/f3 corner of the oscillator then part of the oscillator’s low frequency noise remains unfiltered. Table Communication standards requirements [11]

Standard	Frequency Band (GHZ)	Required Phase Noise (dBc/HZ)
Bluetooth	2.402–2.480	−84 @ 1 MHz
		−114 @ 2 MHz
		−129 @ 3 MHz
GSM900/1800	0.880–0.9601.710–1.880	−122 @ 0.6 MHz
		−132 @ 1.6 MHz
		−139 @ 3 MHz
UMTS	1.920-2.1701.900-2025	−132 @ 3 MHz
		−132 @ 10 MHz
		−144 @ 15 MHz
WiFi	2.412–2.4725.150–5.3505.470–5.825	−102 @ 1 MHz
		−125 @ 25 MHz

Another challenge for the recent RF oscillator designers is the ability to design a wide tuning range oscillator while having low phase noise. The multi-standard applications that are now trending demand such oscillators. The trade-off between the quality factor of the switch capacitor bank that is tuning the LC oscillators and the oscillator’s tuning range is the obstacle in wide tuning-range oscillator design. The MOS transistor switch introduces a resistance that defines the switched capacitor bank’s quality factor in on-state, consequently a lower resistance and so a larger MOS transistor is required for phase noise consideration. However, in the off-state, the series combination of the capacitor in the tank and the switch’s parasitic capacitances defines the equivalent tank capacitance. Consequently a smaller switch is preferred to increase the tuning range. This trade-off makes it impossible to meet both wide tuning range and low phase noise at the same time. For a moderate phase noise, the tuning range of the oscillator can hardly go beyond 50% [13]. Some designers tried to switch inductors or transformers instead of the capacitors in order to increase tuning range, however the equivalent tank’s Q-factor and consequently phase noise is degraded due to the switches in the signal path. Furthermore, due to the reduced oscillation voltage that is tolerable by the nano-metric oxide thickness of advanced technologies CMOS process, the low phase noise design is even more challenging. Figure (a) Analog and; (b) digital phase locked loops [12]. In this book, the main goal is to to elaborate implementation of innovative RF oscillator structures that demonstrate better PN performance, lower cost, and higher power efficiency than the traditional architectures do.

The size, cost, and power consumption of digital circuits are reduced by technology scaling. However, the design of analog and RF circuits faces many difficulties using more advanced CMOS technologies. Consequently, in the semiconductor industry, there are two divergent trends for choosing a technology node for fabricating analog circuits. One trend is to implement analog circuits in an older technology to exploit a higher voltage headroom. This approach is chiefly used in medical, automotive, and high-efficiency lighting applications [14]. Another trend is to implement analog and digital circuits together in the most advanced node such as a 16-nm FinFET. The approach is dictated by the market to achieve highest digital performance with lowest fabrication cost. Figure Oscillator’s open loop and output frequency phase noise. The vision for both wireless cellular communication and the Internet-of-Things keeps moving towards the second strategy [15]. For example, a few years ego IMEC published the first integrated wireless sensor node in 40-nm CMOS including a microcontroller, digital baseband, power management, and BLE transceiver [8]. Furthermore, Intel and DMCE presented a SAW-less HSPA transceiver with on-chip integrated 3G power amplifiers in 65-nm at ISSCC 2015 to enable real low-cost monolithic system integration [16]. Consequently, it is instructive to investigate the effects of technology scaling on the performance of an RF/mm-wave oscillators.

To continue implementing increasingly complex functions while reducing the overall solution costs, scaling of CMOS transistors is inevitable. As circuits become denser, all of the physical dimensions of the transistors must be reduced correspondingly. The SiO2 oxide-layer thickness reduction is accompanied by migrating to smaller supply voltages (see Figure 1.5). This is to maintain the electric field strength across the oxide in order to prevent the device performance degradation due to the time dependent dielectric breakdown (TDDB) [17]. The supply voltage, VDD, is reduced while RF and analog circuits must maintain their dynamic range, noise performance and output power. For example, the oscillator phase noise performance degrades by 6 dB/octave with the reduction of their supply voltage [18]. To compensate this phase noise penalty, the equivalent input parallel resistance of an LC tank should be proportionally decreased by reducing the tank’s inductance. However, the resistance of the tank’s interconnects will start dominating the resonator losses and, consequently, the effective Q-factor and oscillator power efficiency will dramatically drop. Figure Nominal supply voltage versus CMOS technology node for (a) thin-oxide and (b) thick-oxide devices.

Most RF CMOS oscillators employ passive components such as integrated inductors, transformers, and capacitors to realize on-chip LC tanks. Generally, top thick metal layers are used for the realization of inductive components while thinner lower-level metals are exploited in metal-oxide-metal (MoM) capacitors. Note that the 0.18 μm node was the last generation of 8-inch wafer processes with aluminum metallization as almost all modern processes use copper metallization that improves the resistive loss and current handling capability of passive components. Consequently, the quality factor of passives was improved when RF products migrated from 0.18 μm to 0.13 μm technology. By migrating to more advanced nano-scale CMOS technologies, however, the thickness of lower level metals and interlayer dielectric layers reduce correspondingly as shown in Figure 1.6 (a). As a consequence, the physical dimension of a given capacitance becomes smaller but with a worse quality factor (see Figure 1.6 (b)). Fortunately, the thickness of top thick metal layers almost remains constant with scaling. However, the top-metal is closer to the lossy substrate. Hence, the capacitive parasitic, self-resonant frequency, and quality factor of inductor/transformer slightly degrade with scaling as shown in Figure 1.6 (c). Figure (a) Back-end-of-line (BEOL) metallization; quality factor of (b) a 250 fF capacitor, and (c) a 100pH inductor in 65nm and 32 nm CMOS technologies [19]. Figure Damascene process steps [20]. As mentioned above, in most advanced CMOS technologies, copper is used for interconnections due to its low sheet resistance, high maximum current density, high thermal conductivity and resilience to electromigration failures. However, it is difficult to pattern copper using conventional etching techniques. Consequently, unlike traditional metallization of aluminum, copper metallization needs an additional damascene process as shown in Figure 1.7 [20]. The inter-level dielectric is first deposited in the damascene process. Secondly, the dielectric is etched to define trenches where the metal lines will lie. Thirdly, copper is electroplated to fill the patterned oxide trenches. Finally, the surface is planarized and polished to remove surplus copper outside the desired metal lines using chemical-mechanical polishing (CMP). Unfortunately, CMP suffers from dishing and erosion phenomena. Since copper is much softer than the inter-level dielectric, areas with higher metal density are polished much faster than the others. Consequently, the metal thickness of the sparse areas become thicker than that of the dense places as shown in Figure 1.8 (a) [22]. To resolve this issue, a minimum metal density must be satisfied for the entire chip. For example, the minimum metal density must be at least 25% in any 100 μm×100μm square in a 28-nm technology. Hence, inductors and transformers must include dummy metal pieces from the lowest to the highest metal layer (see Figure 1.8 (c)). Metal dummies show negligible effects on the windings self-inductance and the coupling factor. However, as shown in Figure 1.8 (b), eddy currents in dummy fills increase the loss and thus the inductor’s/transformer’s Q-factor could be degraded by 10% [23]. Figure (a) Thickness variation by erosion in the CMP stage; (b) electromagnetic coupling between the wire and dummy fills; (c) inductor/transformer with lots of dummy metal fills. To conclude this section, the quality factor of passives degrades by migrating to more advanced nano-scale CMOS technologies. It leads to a worse phase noise performance for oscillators.

Figure 1.9 (a) shows the normalized input-referred 1/f noise, Svg, versus frequency for different technology nodes. Due to oxide scaling enabled by high-k/metal gate technologies, the normalized Svg is monotonically reduced with each successive technology node. For the same transistor area, Svg decreases ∼10× from the 0.13μm node to 32nm node. However, as shown in Figure 1.9 (b), the excess noise factor of CMOS transistors increases by migrating to finer CMOS technologies. Consequently, oscillator’s core transistors inject more thermal noise to the tank, degrading its phase noise performance. Figure (a) Flicker noise scaling trend; (b) measured excess noise (γ) factor versus drain–source voltage at 10 GHz and Vgs = 1.0 V for different gate lengths of NMOS transistors in 40 nm LP technology [21].

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The oscillators are the only block that is universally used in both transmit and receive paths (see Figure 2.1), and consequently their spectral purity and efficiency highly affect the transceiver performance. The phase noise of the oscillator results in reciprocal mixing in the receive path, where the blocker is mixed with the oscillator’s phase noise and shows itself on top of the desired signal and consequently degrades the receiver sensitivity [1]. This problem especially shows itself in contemporary mobile phones that support 2G, 3G, and 4G modes and WiFi standards with two very close antennas in one device [2], or in wide-band CMOS receivers without off-chip SAW filters, in which blockers can enter the chip without any pre-attenuation [3]. In transmit path, the amplified phase noise of the transmitter’s oscillator can desensitize a nearby receiver [1]. Furthermore, as one of the most power hungry blocks in the transceiver, its power consumption limits the efficiency of the transceiver [4, 5]. Therefore, understanding and modeling the phase noise of an oscillator have been the subject of numerous studies [6–12]. The linear time-variant model through the impulse response of each noise source of the oscillator [10] is the most approached method since its introduction. We are relying on this method to analyze the oscillators in this book; so let us have a quick overview first. The relatively accurate modeling of phase noise in this method is by acknowledging time-variant behavior of the oscillators. To make it more clear, note that a current impulse injected to the tank of Figure 2.2(a) can change oscillation phase and/or amplitude depending on the injection time (see Figure 2.2(b,c)). If the current impulse is injected when oscillation waveform is at its maximum, the oscillation amplitude will be disturbed but the phase will not be. On the other hand, current impulse at the zero-crossings results in a minimum amplitude and maximum phase disturbance. The impulse response is however periodic with respect to injection time. The impulse sensitivity function (ISF), Γ(ω0τ), is defined as a dimensionless, periodic function with period of 2π that describes the oscillation phase shift from injected current impulses during the period [10]. ISF is a periodic function and, consequently, can be written in a Fourier series, Figure A generic RF transceiver [1]. Figure Phase response to an impulse current [10]. Phase modulation is then obtained by convolving the current noise source and ISF as where qmax is the maximum charge displacement at the capacitance of the node that the noise is injected. For a current such as i(t) = In cos[(nω0 + Δω)t], the excess phase can be found as The modulated phase shows itself in the phase noise spectrum since we can write and consequently this injected current results in two sidebands at ω0 ± Δω0 and The same method can be generalized for random noise sources and by applying the Parseval’s relation to derive the phase noise for a white power spectral density noise as, The most accurate method to calculate ISF of each noise source is by simulation. An impulse current should be injected to a node in the circuit at a certain time. The time shift of the oscillation should be measured after a few cycles and be converted to the phase shift. By sweeping the injection time of the current impulse over one oscillation period, ISF can be measured. Very recently, a fast and accurate simulation technique of ISF based on positive sidebands of periodic transfer function (e.g. PXF in Cadence) was revealed in [13]. Upconversion of the device’s 1/f noise to phase noise can also be investigated by this method. If the application demands a low phase noise, the LC oscillator structure should be chosen. The thermal to phase noise upconversion (20 dB/dec region) of these oscillators can be found as where Rt is the equivalent parallel resistance of the tank, k is Boltzmann’s constant, T is the temperature, and , and F is the noise factor and can be found as in which Γi is the ISF of the ith noise source.

The traditional class-B oscillator, of Figure 2.3(a), is widely used in RF applications due to its simplicity and robustness. The noise factor in a class-B structure is ideally equal to γ + 1 [12] if MT tail current transistor is an ideal current source. In this case, not only the current source avoids contributing to phase noise, but it also provides an infinite impedance at the common source of the gm transistors, which, as we explain later, is beneficial for the phase noise reduction. Let us investigate how the performance of this oscillator topology can be improved. The figure of merit (FoM) that is widely used to compare the oscillator performance is The objective is to reduce the phase noise and/or power consumption of the oscillator. Increasing the tank’s quality factor reduces the oscillator’s phase noise. The tank’s quality factor depends on both the inductive and capacitive quality factors: The inductor’s quality factor, QL, which usually limits Qt, is mostly technology-dependent but does not improve with technology scaling. The capacitive quality factor, QC, on the other hand, depends on the tuning range of the oscillator. The switched-capacitor structure shown in Figure 2.4 is often used to tune the conventional oscillators. When Ms is on, , and the switch’s on-resistance, ron defines . To improve Qc, ron and consequently Ms size should increase. However, a larger Ms would add to the parasitic capacitance and consequently would increase the switched-capacitor equivalent capacitance when Ms is off: . Consequently, Qt will be defined by the technology and oscillator’s tuning range, and is rarely a design parameter to substantially improve the phase noise. Figure A class-B oscillator (a) schematic; (b) oscillation amplitude versus tail current; (c) ideal and real drain current waveforms; (d) oscillation voltage waveforms. Another approach to improve the oscillator’s phase noise is by reducing the tank’s inductance while keeping its quality factor the same. Doing so reduces Rt = LωQt; however, it increases the power consumption , with the same rate, and hence FoM will not improve. Furthermore, by reducing the inductor’s size, the tank interconnection losses become more important and, at some point, they will limit its quality factor. This oscillator shows the best performance when its oscillation amplitude is around VDD [14–16] and consequently αV = 1. After this point, the oscillation amplitude stops increasing with the tail current increase (see Figure 2.3(b)) while its power consumption still increases linearly with the tail current, thus reducing the FoM. The drain current of M1,2 transistors has almost a square waveform when the current source is ideal and so (see Figure 2.3(c)). However, in a real scenario, a non-ideal current source will bring up some issues and limitations. First of all, MT transistor will contribute to the phase noise, thus increasing the noise factor beyond 1 + γ. The minimum tail node voltage, VT, is also limited by the need to keep the MT transistor in saturation; consequently the maximum oscillation voltage amplitude reduces to VDD − Vsat and so αV < 1 (αV ≈ 0.8). The capacitance at node T tends to keep its voltage at a constant level. Consequently, for large oscillation amplitudes with M1,2 entering the triode region, the ideal square wave of M1,2 drain current experiences a dimple, as shown in Figure 2.3(c). Hence, αI drops from the ideal value of , and phase noise is increased. On the other hand, when M1 or M2 transistors enter triode region for a portion of oscillation period, they will show a low impedance. Furthermore, the equivalent parasitic capacitance at node T creates a low impedance path to ground. Therefore, the tank finds a discharge path to the ground for the time that either one of these transistors is in the triode region and so its quality factor drops, thus limiting the oscillator’s phase noise. The MT transistor size is usually relatively large in order to reduce its flicker noise. Consequently, the parasitic capacitor at node T is large enough to provide such a low frequency path. However, it is also helpful in partially filtering the MT transistor’s thermal noise. Figure The switch capacitor tuning circuit in on and off states. Various solutions are proposed in the literature to improve the class-B topology phase noise or to improve the oscillator’s phase noise–power consumption trade-off by introducing new classes of oscillations. One of the most effective techniques that could improve the class-B considerably is the noise filtering technique [17]. In this technique, the MT’s thermal noise is filtered by a relatively large capacitor and a high impedance path is inserted between the core transistors and MT to deny any discharge path to the tank. Although this technique is very effective, since the high impedance path is realized by another resonator, it increases the die area significantly. Another interesting technique to improve the oscillator’s phase noise is to couple N oscillator cores together [18]. This technique has been used in microwave circuits [19] and also employed to improve phase noise in RF applications [20]. With coupling N cores, phase noise reduces by a factor of N while the power consumption increases by the same factor. Consequently, although the phase noise is reduced, the FoM remains the same. However, the die area is surely getting N times larger. In the following sections, we briefly review other oscillator topologies that attempt to improve the phase noise-power consumption trade-off in an oscillator. In a class-C structure, M1,2 are biased in a way as to always remain in saturation during the whole oscillation period. In another strategy, the oscillation waveforms in class-D and class-F structures offer special impulse sensitivity functions (ISFs) that prevent circuit noise from upconverting to phase noise.

Class-C structure [21] is shown in Figure 2.5(a). In this class of operation, the core transistors are kept in saturation and, consequently, they show a high impedance during the entire oscillation period. The tank does not find a discharge path to the ground and so its quality factor is preserved. This structure also saves 36% of the power consumption for the same phase noise by changing the square pulses of the M1,2 drain current in class-B operation to narrow and tall pulses with αI = 1. To ensure the saturation region of operation, M1,2 transistor gates are decoupled from the tank’s oscillation voltage and are biased at a value well below the VDD voltage. A large capacitor in parallel with the MT current source allows class-C like tall and narrow current pulses for the M1,2 transistors. Figure (a) A class-C oscillator schematic and (b) its voltage waveforms. However, the maximum oscillation amplitude is limited in this topology. If the oscillation amplitude gets large enough to push M1,2 into triode region, not only the tank’s quality factor heavily drops due to large CT, but also M1,2 drain current will no longer be tall and narrow pulses and αI dramatically drops. Consequently, although the phase noise and power efficiency are improved for low oscillation amplitudes compared to class-B oscillator structure with the same amplitude, the minimum achievable phase noise of this structure is limited. An attempt to increase the class-C swing is done by removing the current source transistor MT and generating Vbias by a current mirror circuit [22]. That oscillator topology also suffers from a tradeoff between its robust start-up and the maximum oscillation voltage in steady state [23]. Vbias should be relatively large to facilitate start-up, but large Vbias values limit the steady-state oscillation amplitude. It was proposed to adjust Vbias dynamically in a negative feedback loop [23–25], which consumes extra power (see Figure 2.6(a)), or to employ class-B switching transistors in parallel with the class-C ones to ensure start-up for low Vbias values [26,27], which reduces αI and consequently power efficiency (see Figure 2.6(b)). The power efficiency of this structure motivated designers in [28] to incorporate this oscillator topology in a Bluetooth low energy (BLE) transmitter. Figure (a) A class-C with dynamic generation of Vbias [23]; (b) a hybrid class-B/class-C oscillator [27]. Interestingly, the inherently low flicker noise operation of class-C has long eluded proper explanation. It was only very recently explained in [13] by applying the principles disclosed in this book.

The schematic of this oscillator topology is shown in Figure 2.7(a). The tail transistor is removed in this structure, eliminating the overhead voltage necessary for the tail current source transistor. Furthermore, M1,2 transistor sizes are chosen large enough to become almost ideal switches. The oscillation voltage amplitude is maximized in this structure and reaches about 3VDD. By doing so, it pushes M1,2 transistors deep into the triode region (even more than in the class-B structure) and, consequently, they generate considerable amount of noise. However, as demonstrated in Figure 2.7(b), the oscillation voltages, V1 or V2, are forced to ground for almost half the period. V1 (V2) is mostly grounded when M1 (M2) is in the triode region, and, consequently, the ISF of node D1 (D2) is almost zero for most of this period, preventing M1 (M2) noise to be upconverted to phase noise. The idea of voltage-switching oscillators was first proposed in 1959 [29] with a discrete BJT implementation, consequently not suitable for RF applications. However, recent CMOS technologies make excellent switches with reasonable sizes available and consequently this structure is attracting an increasing interest [30–32]. The high oscillation amplitude in this structure makes it suitable for low-voltage low-phase-noise applications [32, 33]. The product of the drain current through MOS switches and voltage is almost zero across the oscillation period, consequently the power efficiency of this structure is beyond 90% [31]. However, this oscillator structure not only can work with low voltage supplies but it should utilize low power supply voltages, otherwise the M1,2 transistors, which should be thin-oxide devices to guarantee nearly ideal switching, will face breakdown. Another limitation of the class-D structure is its relatively high upconversion of low-frequency noise as well as high supply pushing. It has been tried to minimize this problem by an on-chip LDO in [34], but it is power consuming. We elaborate this problem in detail in Chapter 5 and then disclose a solution. Figure (a) A class-D oscillator schematic and (b) its voltage waveforms.

If the ISF of a certain oscillation waveform is negligible for some amount of oscillation period, the circuit noise cannot be upconverted to phase noise during that time, which is beneficial in reducing the oscillator’s phase noise. Class-F oscillators realize such oscillation waveforms by giving rise to either third or second harmonic of oscillation voltage [35–39]. This class of oscillators is discussed in detail in Chapters 3 and 4.

In this chapter, we briefly introduced different oscillator structures and mentioned their benefits and drawbacks. We discussed the nonidealities that the traditional class-B oscillators face and reviewed how each structure tries to overcome them. Class-C oscillators improve phase noise for the same power consumption but only when the oscillation amplitude is low enough to keep the core transistors in saturation. Class-D oscillators offer a very low noise without requiring large supply voltages, but they are limited to low supply voltages due to reliability concerns. Class-F oscillators create waveforms with a special ISF that prevents conversion from the circuit thermal noise to phase noise.

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An oscillator topology demonstrating an improved phase noise performance is introduced and analyzed in this chapter. It exploits a time-variant phase noise model with insights into the phase noise conversion mechanisms. This oscillator enforces a pseudo-square voltage waveform around the LC tank by increasing the third harmonic of the fundamental oscillation voltage through an additional impedance peak. This auxiliary impedance peak is realized by a transformer with moderately coupled resonating windings. As a result, the effective impulse sensitivity function (ISF) decreases, thus reducing the oscillator’s effective noise factor such that a significant improvement in the oscillator phase noise and power efficiency is achieved. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators’ structures shows that the class-F3 exhibits the lowest phase noise at the same tank’s quality factor and supply voltage. The prototype of the class-F3 oscillator is implemented in TSMC 65-nm standard CMOS. It exhibits average phase noise of −142 dBc/Hz at 3 MHz offset from the carrier over 5.9–7.6 GHz tuning range with figure of merit of 192 dBc/Hz. The oscillator occupies 0.12 mm2 while drawing 12 mA from 1.25 V supply.

Designing voltage-controlled and digitally controlled oscillators (VCO, DCO) of high spectral purity and low power consumption is quite challenging, especially for GSM transmitter (TX), where the oscillator phase noise must be less than −162 dBc/Hz at 20 MHz offset frequency from 915 MHz carrier [1]. At the same time, the RF oscillator consumes disproportionate amount of power of an RF frequency synthesizer [2, 3] and burns more than 30% of the cellular RX power [4, 5]. Consequently, any power reduction of RF oscillators will greatly benefit the overall transceiver power efficiency and ultimately the battery lifetime. This motivation has encouraged an intensive research to improve the power efficiency of an RF oscillator while satisfying the strict phase noise requirements of the cellular standards. Figure Oscillator schematic: (a) traditional class-B; (b) class-C. The traditional class-B oscillator (Figure 3.1(a)) is the most prevalent architecture due to its simplicity and robustness. However, as shown in Chapter 2, its phase noise and power efficiency performance drops dramatically by replacing the ideal current source with a real one. For the best performance, the oscillation amplitude should be near supply voltage VDD [6, 7]. Therefore, the gm-devices M1/2 enter deep triode for part of the oscillation period. The low impedance path between node “T” due to MT together with M1/2 entering deep triode degrades Q-factor of the tank dramatically and phase noise improvement by increasing oscillation voltage would be negligible. The noise filtering technique [8] provides a relatively high impedance between the gm-devices and the current source. Hence, the structure maintains the intrinsic Q-factor of the tank during the entire oscillation period. However, it requires an extra resonator sensitive to parasitic capacitances, increasing the design complexity, area, and cost. As we discussed in Chapter 2, the class-C oscillator (Figure 3.1(b)) prevents the gm-devices from entering the triode region [9, 10]. Hence, the tank Q-factor is preserved throughout the oscillation period. By changing the drain current shape to the “tall and narrow” form for the class-C operation, the oscillator saves 36% power. However, the constraint of avoiding entering the triode region limits the maximum oscillation amplitude of the class-C oscillator to around VDD/2, for the case of bias voltage VB as low as a threshold voltage of the active devices, which limits the lowest achievable phase noise performance. Harmonic tuning oscillator enforces a pseudo-square voltage waveform around the LC tank through increasing the third harmonic component of the fundamental oscillation voltage through an additional tank impedance peak at that frequency. Kim et al. [11] exploited this technique to improve the phase noise performance of the LC oscillator by increasing the oscillation zero-crossings’ slope. However, that structure requires more than two separate LC resonators to make the desired tank input impedance. It increases die area and cost and decreases tuning range due to larger parasitics. Furthermore, the oscillator transconductance loop gain is the same for both resonant frequencies, thus raising the probability of undesired oscillation at the auxiliary tank input impedance. Here, we show how to resolve the concerns and quantify intuitively and theoretically the phase noise and power efficiency improvement of the class-F3 oscillator compared to other structures [12, 13, 31]. The chapter is organized as follows: Section 3.2 establishes the environment to introduce the class-F3 oscillator. The circuit-to-phase-noise conversion mechanisms are studied in Section 3.3. Section 3.4 presents extensive measurement results of the prototype, while Section 3.5 wraps up this chapter with conclusions.

Suppose the oscillation voltage around the tank was a square wave instead of a sinusoidal. As a consequence, the oscillator would exploit the special ISF [14] properties of the square-wave oscillation voltage to achieve a better phase noise and power efficiency. However, the gm-devices would work in the triode region (shaded area in Figure 3.2(b)) even longer than in the case of the sinusoidal oscillator. Hence, the loaded resonator and gm-device inject more noise to the tank. Nevertheless, ISF value is expected to be negligible in this time span due to the zero derivative of the oscillation voltage [14]. Although the circuit injects huge amount of noise to the tank, the noise cannot change the phase of the oscillation voltage and thus there is no phase noise degradation. Figure LC-tank oscillator: (a) noise sources; (b) targeted oscillation voltage (top) and its expected ISF (bottom).

The above reasoning indicates that the square-wave oscillation voltage has special ISF properties that are beneficial for the oscillator phase noise performance. But how can a square wave be realized across the tank? Let us take a closer look at the traditional oscillator in the frequency domain. As shown in Figure 3.3, the drain current of a typical LC-tank oscillator is approximately a square wave. Hence, it ideally has a fundamental and odd harmonic components. On the other hand, the tank input impedance has a magnitude peak only at the fundamental frequency. Therefore, the tank filters out the harmonic components of the drain current and finally a sinusoidal wave is seen across the tank. Now, suppose the tank offers another input impedance magnitude peak around the third harmonic of the fundamental frequency (see Figure 3.4). The tank would be prevented from filtering out the third harmonic component of the drain current. Consequently, the oscillation voltage will contain a significant amount of the third harmonic component in addition to the fundamental: Figure Traditional oscillator waveforms in time and frequency domains. Figure New oscillator’s waveforms in time and frequency domains. ζ is defined as the magnitude ratio of the third-to-first harmonic components of the oscillation voltage. where Rp1 and Rp3 are the tank impedance magnitudes at the main resonant frequency ω1 and 3ω1, respectively. Figure 3.5 illustrates the oscillation voltage and its related expected ISF function (based on the closed-form equation in [14]) for different ζ values. The ISF rms value of the new oscillation waveform can be estimated by the following expression for −π/8 < Δϕ < π/8: The waveform would become a sinusoidal for the extreme case of ζ = 0, ∞, so (3.3) predicts , which is well known for the traditional oscillators. reaches its lowest value of 1/4 for ζ = 1/3, translated to a 3-dB phase noise and FoM improvement compared to the traditional oscillators. Furthermore, ISF of the new oscillator is negligible while the circuit injects significant amount of noise to the tank. Consequently, the oscillator FoM improvement could be larger than that predicted by just the ISF rms reduction.

The argumentation related to Figure 3.4 advocates the use of two resonant frequencies with a ratio of 3. The simplest way of realizing that would be with two separate inductors [11, 15]. However, this will be bulky and inefficient. The chosen option in this work is a transformer-based resonator. The preferred resonator consists of a transformer with turns ratio n and tuning capacitors C1 and C2 at the transformer’s primary and secondary windings, respectively (see Figure 3.6). Equation (3.4) expresses the exact mathematical equation of the input impedance of the tank. Figure The effect of adding third harmonic in the oscillation waveform (top) and its expected ISF (bottom). Figure Transformer-based resonator (a) and its equivalent circuit (b). where km is the magnetic coupling factor of the transformer, rp and rs model the equivalent series resistance of the primary Lp and secondary Ls inductances [16]. The denominator of Zin is a fourth-order polynomial for the imperfect coupling factor (i.e., km < 1). Hence, the tank contains two different conjugate pole pairs, which realize two different resonant frequencies. Consequently, the input impedance has two magnitude peaks at these frequencies. Note that both resonant frequencies can satisfy the Barkhausen criterion with a sufficient loop gain [17]. However, the resulting multi-oscillation behavior is undesired and must be avoided [18]. In our case, it is preferred to see an oscillation at the lower resonant frequency ω1 and the additional tank impedance at ω2 is used to make a pseudo-square waveform across the tank. These two possible resonant frequencies can be expressed as The following expression offers a good estimation of the main resonant frequency of the tank for 0.5 ≤ km ≤ 1. However, we are interested in the ratio of resonant frequencies as given by where X-factor is defined as Equation (3.7) indicates that the resonant frequency ratio ω2/ω1 is just a function of the transformer inductance ratio Ls/Lp, tuning capacitance ratio C2/C1, and transformer magnetic coupling factor km. The relative matching of capacitors (and inductors) in today’s CMOS technology is expected to be much better than 1%, while the magnetic coupling is controlled through lithography that precisely sets the physical dimensions of the transformer. Consequently, the relative position of the resonant frequencies is not sensitive to the process variation. The ω2/ω1 ratio is illustrated versus X-factor for different km in Figure 3.7. As expected, the ratio moves to higher values for larger km and finally the second resonance disappears for the perfect coupling factor. The ratio of ω2/ω1 reaches the desired value of 3 at two points for the coupling factor of less than 0.8. Both points put ω2 at the correct position of 3ω1. However, the desired X-factor should be chosen based on the magnitude ratio Rp2/Rp1 of the tank input impedance at resonance. The sum of the even orders of the denominator in (3.4) is zero at resonant frequencies. It can be shown that the first-order terms of the numerator and the denominator are dominant at ω1. By using (3.6), assuming Qp = Lpω/rp, Qs = Lsω/rs, the tank input impedance at the fundamental frequency is expressed as Figure Ratio of the tank resonant frequencies versus X-factor for different km. On the other hand, it can be shown that the third-order terms of the numerator and the denominator are dominant in (3.4) at ω2 = 3ω1. It follows that Rp2 is a strong function of the coupling factor of the transformer and thus the resulting leakage inductance. Weaker magnetic coupling will result in higher impedance magnitude at ω2 and, consequently, the second resonance needs a lower transconductance gain to excite. It could even become a dominant pole and the circuit would oscillate at ω2 instead of ω1. This phenomenon has been used to extend the oscillator tuning range in [17, 19], and [20]. As explained before, Rp2/Rp1 controls the amount of the third harmonic component of the oscillation voltage. The impedance magnitude ratio is equal to Figure The transformer-based tank characteristics: (a) the input impedance, Zin magnitude; (b) the trans-impedance, Z21 magnitude; (C) transformer’s secondary to primary voltage gain; (d) the phase of Zin and Z21 (momentum simulation). Hence, the smaller X-factor results in lower tank equivalent resistance at ω2 = 3ω1. Thus, the tank filters out more of the third harmonic of the drain current and the oscillation voltage becomes more sinusoidal. Figure 3.8(a) illustrates momentum simulation results of Zin of the transformer-based tank versus frequency for both X-factors that satisfy the resonant frequency ratio of 3. The larger X-factor offers significantly higher tank impedance at ω2, which is entirely in agreement with the theoretical analysis. The X-factor is defined as a product of the transformer inductance ratio Ls/Lp and tuning capacitance ratio C2/C1. This leads to a question of how to best divide X-factor between the inductance and capacitance ratios. In general, larger Ls/Lp results in higher inter-winding voltage gain, which translates to sharper transition at zero-crossings and larger oscillation amplitude at the secondary winding. Both of these effects have a direct consequence on the phase noise improvement. However, the transformer Q-factor drops by increasing the turns ratio. In addition, very large oscillation voltage swing brings up reliability issues due to the gate-oxide breakdown. It turns out that the turns ratio of 2 can satisfy the aforementioned constraints altogether.

The transformer-based resonator, whose schematic was shown in Figure 3.6, offers a filtering function on the signal path from the primary to the secondary windings. The tank voltage gain is derived as Bode diagram of the tank voltage gain transfer function is shown in Figure 3.9. The tank exhibits a 20 dB/dec attenuation for frequencies lower than the first pole and offers a constant voltage gain at frequencies between the first pole and the complex conjugate pole pair at ωp. The gain plot reveals an interesting peak at frequencies around ωp, beyond which the filter gain drops at the −40 dB/dec slope. The low frequency pole is estimated by By substituting rp = Lpω/Qp, rs = Lsω/Qs and assuming Qp · Qs ≫ 1, the tank gain transfer function can be simplified to the following equation for the frequencies beyond ωp1: Figure Typical secondary-to-primary winding voltage gain of the transformer-based resonator versus frequency. The main characteristics of the tank voltage gain can be specified by considering it as a biquad filter. where The peak frequency is estimated by Qf represents the amount of gain jump around ωp and expressed by Hence, the maximum voltage gain is calculated by Equation (3.19) and Figure 3.9 demonstrate that the transformer-based resonator can offer the voltage gain above kmn at the frequencies near ωp for km < 1 and the peak magnitude is increased by improving Q-factor of the transformer individual inductors. Consequently, ω1 should be close to ωp to have higher passive gain at the fundamental frequency and more attenuation at its harmonic components. Equations (3.6) and (3.17) indicate that ωp is always located at frequencies above ω1 and the frequency gap between them decreases with greater X-factor. Figure 3.8(c) illustrates the voltage gain of the transformer-based tank for two different X-factors that exhibit the same resonant frequencies. The transformer peak gain happens at much higher frequencies for the smaller X-factor and, therefore, the gain is limited to only kmn (2 dB in this case) at ω1. However, X-factor is around 3 for the new oscillator and, as a consequence, ωp moves lower and much closer to ω1. Now, the tank offers higher voltage gain (G1 = 6 dB in this case) at the main resonance and more attenuation (G2 = −7 dB) at ω2. This former translates to larger oscillation voltage swing and thus better phase noise. Table Normalized zero-crossing slope of the novel oscillator

	Normalized Zero-crossing Slope
Traditional LC	1
Novel tank (primary)	1 + 3ζ = 1 + 3 · 1/6 = 1.5
Novel tank (secondary)	G1-3G2ζ = 2.1 − 3 · 0.4 · 1/6 = 1.9

As can be seen in Figure 3.8(d), the input impedance Zin phase is zero at the first and second resonant frequencies. Hence, any injected third harmonic current has a constructive effect resulting in sharper zero-crossings and flat peak for the transformer’s primary winding voltage. However, the tank trans-impedance, Z21 phase shows a 180 degree phase difference at ω1 and ω2 = 3ω1. Consequently, the third harmonic current injection at the primary windings leads to a slower zero-crossings slope at the transformer’s secondary, which has an adverse outcome on the phase noise performance of the oscillator. Figure 3.8(a–c) illustrates that this transformer-based resonator effectively filters out the third harmonic component of the drain current at the secondary winding in order to minimize these side effects and zero-crossings are sharpened by tank’s voltage gain (G1) at ω1. Table 3.1 shows that the zero-crossing slope of this oscillator at both transformer’s windings are improved compared to the traditional oscillator for the same VDD, which is translated to shorter commutating time and lower active device noise factor.

The desired tank impedance, inductance, and capacitance ratios were determined above to enforce the pseudo-square-wave oscillation voltage around the tank. Now, two transistors should be customarily added to the transformer-based resonator to sustain the oscillation. There are two options, however, as shown in Figure 3.10, for connecting the transformer to the active gm-devices. The first option is a transformer-coupled class-F3 oscillator in which the secondary winding is connected to the gate of the gm-devices. The second option is a cross-coupled class-F3 oscillator with a floating secondary transformer winding, which only physically connects to tuning capacitors C2. The oscillation voltage swing, the equivalent resonator quality factor, and tank input impedance are the same for both options. However, the gm-device sustains larger voltage swing in the first option. Consequently, its commutation time is shorter and the active device noise factor is lower. In addition, the gm-device generates higher amount of the third harmonic, which results in sharper pseudo-square oscillation voltage with lower ISF rms value. The second major difference is about the possibility of oscillation at ω2 instead of ω1. The root-locus plot in Figure 3.11 illustrates the route of pole movements towards zeros for different values of the oscillator loop transconductance gain (Gm). As can be seen in Figure 3.11(b), both resonant frequencies (ω1, ω2) can be excited simultaneously with a relatively high value of Gm for the cross-coupled class-F3 oscillator of Figure 3.10(b). It can increase the likelihood of the undesired oscillation at ω2. However, the transformer-coupled circuit of Figure 3.10(a) demonstrates a different behavior. The lower frequency conjugate pole pair moves into the right-hand plane by increasing the absolute value of Gm, while the higher poles are pushed far away from imaginary axis (see Figure 3.11(a)). This guarantees that the oscillation can only happen at ω1. Consequently, it becomes clear that the transformer-coupled oscillator is a better option due to its phase noise performance and the guaranty of operation at the right resonant frequency. Nevertheless, the gate parasitic capacitance appears at the drain through a scaling factor of n2, which reduces its tuning range somewhat as compared to the cross-coupled candidate. Figure Two options of the transformer-based class-F3 oscillator: (a) transformer-coupled and (b) cross-coupled. The first option was chosen as more advantageous in this work. Figure Root-locus plot of the transformer-based class-F3 oscillator: (a) transformer-coupled structure of Figure 3.10(a); and (b) cross-coupled structure of Figure 3.10(b). Figure 3.12(a) illustrates the unconventional oscillation voltage waveforms of this transformer-coupled class-F3 oscillator. As specified in Section 3.2.3, the third harmonic component of the drain voltage attenuates at the gate and thus a sinusoidal wave is seen there. The gate-drain voltage swing goes as high as 2.7·VDD due to the significant voltage gain of the tank. Hence, using thick-oxide gm-devices is a constraint to satisfy the time-dependent dielectric breakdown (TDDB) issue for less than 0.01% failure rate during 10 years of the oscillator operation [21, 22]. The costs are larger parasitics capacitance and slightly lower frequency tuning range. The frequency tuning requires a bit different consideration in the class-F3 oscillator. Both C1 and C2 must, at a coarse level, be changed simultaneously to maintain LsC2/LpC1 ratio such that ω2 aligns with 3ω1. Figure 3.12(b) shows the transient response of the class-F oscillator. At power up, the oscillation voltage is very small and the drain current pulses have narrow and tall shape. Even though the tank has an additional impedance at 3ω1, the third harmonic component of the drain current is negligible and, consequently, the drain oscillation resembles a sinusoid. At steady state, gate oscillation voltage swing is large and the gm-device drain current is square wave. Consequently, the combination of the tank input impedance with significant drain’s third harmonic component results in the pseudo-square-wave for the drain oscillation voltage. This justifies its “class-F3” designation. Figure (a) Oscillation voltage waveforms and (b) transient response of the class-F3 oscillator.

The Q-factor of the complex tank, which comprises two coupled resonators, does not appear to be as straightforward in intuitive understanding as the Q-factor of the individual physical inductors. It is, therefore, imperative to understand the relationship between the open-loop Q-factor of the tank versus the Q-factor of the inductive and capacitive parts of the resonator. First, suppose the tuning capacitance losses are negligible. Consequently, the oscillator equivalent Q-factor just includes the tank’s inductive part losses. The open-loop Q-factor of the oscillator is defined as ω0/2 · dϕ/dω, where ω0 is the resonant frequency and dϕ/dω denotes the slope of the phase of the oscillator open-loop transfer function [23]. To determine the open-loop Q, we need to break the oscillator loop at the gate of M1, as shown in Figure 3.13. The open-loop transfer function is thus given by Figure Open-loop circuit for unloaded Q-factor calculation (a); its equivalent circuit (b). where , B = C1C2 (Lsrp + Lprs), C = LpC1 + LsC2 + rprsC1C2, and D = rpC1 + rsC2. After carrying out lengthy algebra and considering (1 − Cω2 + Aω4 ≈ 0) at the resonant frequencies, Substituting A, B, C, and D into (3.21), then swapping rp and rs with Lpω/Qp and Lsω/Qs, respectively, and assuming QpQs ≫ 1, we obtain Substituting (3.5) as ω into the above equation and carrying out the mathematics, the tank’s inductive part Q-factor at the main resonance is To help with an intuitive understanding, let us consider a boundary case. Suppose that C2 is negligible. Therefore, X-factor is zero and (3.23) predicts that the Qi equals to Qp. This is not surprising because no energy would be stored at the transformer’s secondary winding and its Q-factor would not have any contribution to the equivalent Q-factor of the tank. In addition, (3.23) predicts that the equivalent Q-factor of the tank’s inductive part can exceed Q-factors of the individual inductors. This clearly proves Q-factor enhancement over that of the transformer’s individual inductors. The maximum tank’s inductive part Q-factor is obtained at the following X-factor for a given km, Qp, and Qs. For a typical case of Qs = Qp = Q0, the maximum Qi at ω1 is calculated by The above equation indicates that the equivalent Q-factor of the inductive part of the transformer-based resonator can be enhanced by a factor of 1 + km at the optimum state. However, it does not necessarily mean that the Q-factor of the transformer-based tank generally is superior to the simple LC resonator. The reason is that it is not possible to optimize the Q-factor of both windings of a 1:n transformer at a given frequency and one needs to use lower metal layers for the transformer cross connections, which results in more losses and lower Q-factor [24, 25]. For this prototype, the X-factor is around 3 with km = 0.7 and the simulated Qp and Qs are 14 and 20, respectively. Based on (3.23), the equivalent Q-factor of the inductive part of the tank would be about 26, which is higher than that of the transformers’ individual inductors. The Q-factor of the switched capacitance largely depends on the tuning range (TR) and operating frequency of the oscillator and is about 42 for the TR of 25% at 7 GHz resulting in an average Q-factor of 16 for the tank in this design.

According to the linear time-variant model [14], the phase noise of the oscillator at an offset frequency Δω from its fundamental frequency is expressed as where qmax is the maximum charge displacement across the tuning capacitor C and NL,i is the effective noise produced by ith device given by where is the white current noise power density of the ith noise source, Γi is its relevant ISF function from the corresponding ith device noise, and N is the number of resonators in the oscillator. N is considered one for single-ended and two for differential oscillator topologies with a single LC tank [7]. Figure 3.14 illustrates the major noise sources of CMOS class-B, class C, and class-F3 oscillators. Rp and Gds1,2(t) represent the equivalent tank parallel resistance and channel conductance of the gm transistors, respectively. On the other hand, Gm1,2 and GmT model the noise due to transconductance gain of active core and current source transistors, respectively. By substituting (3.27) into (3.26) and carrying out algebra, the phase noise equation is simplified to Figure RF CMOS oscillator noise sources. where Qt is the tank’s equivalent quality factor and Vp is the maximum oscillation voltage amplitude, derived by where αI is the current conversion efficiency of the oscillator, expressed as the ratio of the fundamental component of gm-devices drain current to dc current IB of the oscillator. F in (3.28) is the effective noise factor of the oscillator, expressed by Suppose that CT is large enough to filter out the thermal noise of the tail transistor. Consequently, F consists of the noise factor of the tank (Ftank), transistor channel conductance (FGDS), and gm of core devices (FGM). The expressions of Ftank and FGDS are where GDSEF1 is the effective drain–source conductance of one of the gm-devices expressed by where GDS1[k] describes the kth Fourier coefficient of the instantaneous conductance, Gds1(t) [26]. FGM can be calculated by Now, the effective negative transconductance of the oscillator needs to overcome the tank and its own channel resistance losses and, therefore, the noise due to GM also increases. where A is the voltage gain of feedback path between the tank and MOS gate. By substituting (3.35) into (3.34) Consequently, the effective noise factor of the oscillator is given by This is a general result and is applicable to the class-B, class-C, and class-F3. The oscillator FoM normalizes the phase noise performance to the oscillation frequency and power consumption, yielding where αV is the voltage efficiency, defined as VP/VDD. To get a better insight, the circuit-to-phase-noise mechanism, relative phase noise, and power efficiency of different oscillator classes are also investigated and compared together in this section. Figure 3.15(a–f) shows the oscillation voltage and drain current for the traditional, class-C and class-F oscillators for the same VDD (i.e., 1.2 V), tank Q-factor (i.e., 15), and RP (i.e., 220 Ω). Figure Mechanisms of circuit noise to phase noise conversion in different classes of RF CMOS oscillator. The αV must be around 0.8 for the class-B and class-F3 oscillators due to the voltage drop Vdsat across the tail transistor needed to keep it in saturation. The combination of the tail capacitance and entering the gm-devices into the linear region reduces αI of class-B from the theoretical value of 2/π to around 0.55. Fortunately, αI is maintained around 2/π for class-F3 due to the pseudo-square drain voltage and larger gate amplitude. The class-C oscillator with a dynamic bias of the active transistor offers significant improvements over the traditional class-C and maximizes the oscillation amplitude without compromising the robustness of the oscillator start-up [27]. Nevertheless, its αV is around 0.7 to avoid gm-devices entering the triode region. Class-C drain current composed of tall and narrow pulses results in αI equal to 0.9 (ideally 1). Obtaining the ISF function is the first step in the calculation of the oscillator’s effective noise factor. The class-B/C ISF function is a sinusoid in quadrature with the tank voltage [7, 28]. However, finding the exact equation of class-F3 ISF is not possible; hence, we had to resort to painstakingly long CadenceTM simulations to obtain the ISF curves. Figure 3.15(g) shows the simulated class-F tank equivalent ISF function, which is smaller than the other classes for almost the entire oscillation period. Figure 3.15(h) demonstrates the tank effective noise factor along the oscillation period for different oscillator classes. The FRP is 32% lower for this class-F3 due to its special ISF properties. The gm-device M1 channel conductance across the oscillation period is shown in Figure 3.15(i). As expected, GDS1(t) of class-F3 exhibits the largest peak due to high oscillation swing at the gate and, consequently, injects more noise than other structures to the tank. On the other hand, class-C operates only in the saturation region and its effective transistor conductance is negligible. Figure 3.15(j) strongly emphasizes that the gm-device resistive channel noise could even be 7 times higher than the tank noise when the M1 operates in the linear region. To get a better insight, one need to simultaneously focus on Figures 3.15(j) and (k). Although the class-F3 GDS1 generates lots of noise in the second half of the period, its relevant ISF value is very small there. Hence, the excessive transistor channel noise cannot convert to the phase noise and as shown in Figure 3.15(l), the FGDS of class-F3 is one-half of the traditional oscillator. The transconductance loop gains of the different oscillator structures are shown in Figure 3.15(m). Class-F3 needs to exhibit the highest effective transconductance loop gain to compensate its larger gm-devices channel resistance losses. However, half of the required loop gain is covered by the transformer-based tank voltage gain. Figure 3.15(o) demonstrates the active device effective noise factor along the oscillation period. Class-F3 offers the lowest FGM due to its special ISF nature and the passive voltage gain between the tank and gate of the gm-transistors. Table Comparison of different oscillator’s classes for the same VDD (1.2 V), tank Q-factor (15), RP (i.e. 220 Ω), and carrier frequency (7 GHz) at 3 MHz offset frequency

	Theoretical Expression	Class-B	Class-C	Class-F3
FRP		1 (average)	1 (average)	0.7 (best)
FGDS		0.56 (worst)	0.07 (best)	0.27 (average)
FGM		1.56γ (worst)	1.07γ (average)	0.7γ (best)
F		5.5dB (worst)	3.9 dB (average)	2.8 dB (best)
αI	IH1/IB	0.55 (worst)	0.9 (best)	0.63 (average)
αV	Vp/VDD	0.8 (best)	0.7 (average)	0.8 (best)
PN(dBc/Hz)		−133.5 (worst)	−134 (average)	−136 (best)
FoM (dB)		191.2 (worst)	194.5 (best)	194.2(≈best)

Table 3.2 summarizes the performance of different oscillator classes of this example. It can be concluded that class-F3 oscillator achieves the lowest circuit-to-phase-noise conversion along the best phase noise performance with almost the same power efficiency as the class-C oscillator. The use of transformer in the class-F3 configuration offers an additional reduction of the 1/f3 phase noise corner. The transformer inherently rejects the common-mode signals. Hence, the 1/f noise of the tail current source can appear at the transformer’s primary, but it will be effectively filtered out on the path to the secondary winding. Consequently, the AM-to-PM conversion at the C2 switched capacitors is entirely avoided.

Figure 3.16(a) illustrates the tank input impedance magnitude and phase for the imperfect position of the second resonance frequency ω2. A 6% mismatch is applied to the C2/C1 ratio, which shifts ω2 to frequencies higher than 3ω1. Hence, the third harmonic of the drain current is multiplied by a lower impedance magnitude with a phase shift resulting in a distorted pseudo-square oscillation waveform as shown in Figure 3.16(b). Intuitively, if the Q-factor at ω2 was smaller, the tank impedance bandwidth around it would be wider. Therefore, the tank input impedance phase shift and magnitude reduction would be less for a given ω2 drift from 3ω1. As a consequence, the oscillator would be less sensitive to the position of ω2 and thus the tuning capacitance ratio. Based on the open-loop Q-factor analysis, substituting ω2 ≈ 9/(LsC2 + LpC1) into (3.22), the Qi is obtained as 0.3Q0 at ω2. Fortunately enough, the proposed tank configuration automatically reduces the equivalent tank Q-factor at ω2 to 30% of the main resonance Q-factor. This is completely in line with the desire to reduce the sensitivity to the position of ω2 in class-F3. Consequently, a realistic example ±30 fF variation in C1 from its optimum point has absolutely no major side effects on the oscillator waveform and thus its phase noise performance, as apparent from Figure 3.16. It is strongly emphasized that the circuit oscillates based on ω1 resonance, and low Q-factor at ω2 has no adverse consequence on the oscillator phase noise performance. Figure Sensitivity of class-F3 oscillator to the position of the second resonant frequency: tank’s input impedance magnitude and phase (top); oscillation waveform (bottom).

The class-F3 oscillator, whose schematic was shown in Figure 3.10(a), has been realized in TSMC 1P7M 65-nm CMOS technology with Alucap layer. The differential transistors are thick-oxide devices of 12(4-μm/0.28-μm) dimension to withstand large gate voltage swing. However, the tail current source MT is implemented as a thin-oxide 500-μm/0.24-μm device biased in saturation. The large channel length is selected to minimize its 1/f noise. Its large drain–bulk and drain–gate parasitic capacitances combined with CT = 2 pF MOM capacitor shunt the MT thermal noise to ground. The step-up 1:2 transformer is realized by stacking the 1.45 μm Alucap layer on top of the 3.4 μm thick top (M7 layer) copper metal. Its primary and secondary differential self-inductances are about 500 and 1500 pH, respectively, with the magnetic coupling factor of 0.73. The transformer was designed with a goal of maximizing Q-factor of the secondary winding, Qs, at the desired operating frequency. Based on (3.23), Qs is the dominant factor in the tank equivalent Q-factor expression, provided (LsC2)/(LPC1) is larger than one, which is valid for this oscillator prototype. In addition, the oscillation voltage is sinusoidal across the secondary winding. It means the oscillator phase noise is more sensitive to the circuit noise at the secondary winding compared to the primary side with the pseudo-square waveform. Four switched MOM capacitors BC0 − BC3 placed across the secondary winding realize coarse tuning bits, while the fine control bits BF0 − BF3 with LSB size of 20 fF adjust the position of ω2 near 3ω1. The center tap of the secondary winding is connected to the bias voltage, which is fixed around 1 V to guarantee safe oscillator start-up in all process corners. A resistive shunt buffer interfaces the oscillator output to the dynamic divider [2]. A differential output buffer drives a 50-Ω load. The separation of the oscillator core and divider/output buffer voltage supplies and grounds serves to maximize the isolation between the circuit blocks. The die micrograph is shown in Figure 3.17. The oscillator core die area is 0.12 mm2.

The measured phase noise at 3.7 GHz (after the on-chip ÷2 divider) at 1.25 V and 12 mA current consumption is shown in Figure 3.18. The phase noise of −142.2 dBc/Hz at 3 MHz offset lies on the 20 dB/dec slope, which extrapolates to −158.7 dBc/Hz at 20 MHz offset (−170.8 dBc/Hz when normalized to 915 MHz) and meets the GSM TX mobile station (MS) specification with a very wide 8 dB margin. The oscillation purity of the class-F3 oscillator is good enough to compare its performance to cellular basestation (BTS) phase noise requirements. The GSM/DCS “Micro” BTS phase noise requirements are easily met. However, the phase noise would be off by 3 dB for the toughest DCS-1800 “Normal” BTS specification at 800 kHz offset frequency [29]. The 1/f3 phase noise corner is around 700 kHz at the highest frequency due to the asymmetric layout of the oscillator differential nodes further magnified by the dominance of parasitics in the equivalent tank capacitance. The 1/f3 phase noise corner moves to around 300 kHz at the middle and low parts of the tuning range. The noise floor is −160 dBc/Hz and dominated by thermal noise from the divider and buffers. The oscillator has a 25% tuning range from 5.9 to 7.6 GHz. Figure 3.19(a) shows the average phase noise performance of four samples at 3 MHz offset frequency across the tuning range (after the divider), together with the corresponding FoM. The average FoM is as high as 192 dBc/Hz and varies about 2 dB across the tuning range. The divided output frequency versus supply is shown in Figure 3.19(b) and reveals very low frequency pushing of 50 and 18 MHz/V at the highest and lowest frequencies, respectively. Figure Die photograph of class-F3 oscillator. Figure Measured phase noise at 3.7 GHz and power dissipation of 15 mW. Specifications (MS: mobile station; BTS: basestation) are normalized to the carrier frequency. Figure (a) Phase noise and figure of merit (FoM) at 3 MHz offset versus carrier frequency and (b) frequency pushing due to supply voltage variation. The phase noise of the class-F3 oscillator was measured at the fixed frequency of 3.5 GHz for two configurations. In the first configuration, the C2/C1 ratio was set to one to align the second resonant frequency ω2 exactly at the third harmonic of the fundamental frequency ω1. This is the optimum configuration of the class-F3 oscillator (Figure 3.20, top). In the second configuration, the oscillation frequency is kept fixed, but an unrealistically high 40% mismatch was applied to the C2/C1 ratio, which lowers ω2, in order to see its effects on the phase noise performance (see Figure 3.20, bottom). As a consequence, the third harmonic component of the drain oscillation voltage is reduced and a phase shift can be seen between voltage waveform components at 3ω1 and ω1. Therefore, its ISF rms value is worse than optimum, thus causing a 2-dB phase noise degradation in the 20-dB/dec region. In addition, the voltage waveform demonstrates more asymmetry in the rise and fall times, which translates to the non-zero ISF dc value and increases the upconversion factor of the 1/f noise corner of gm-devices. As can be seen in Figure 3.20, the 1/f3 phase noise corner is increased by 25% or 100 kHz in the non-optimum case. It results in a 3-dB phase noise penalty in the flicker noise region. Figure Measured phase noise at 3.5 GHz and simulated oscillation waveforms: (a) optimum case; (b) exaggerated non-optimum case. Table 3.3 summarizes performance of this class-F3 oscillator and compares it with the relevant oscillators. The class-F3 demonstrates a 5-dB phase noise and 7-dB FoM improvements over the traditional commercial oscillator [2] with almost the same tuning range. For the same phase noise performance range (−154 to −155 dBc/Hz) at 3-MHz offset for the normalized 915-MHz carrier, the class-F3 oscillator consumes only 15 mW, which is much lower than that with Colpitts [30], class B/C [10], and clip-and-restore [29] topologies. Only the noise-filtering-technique oscillator [8] offers a better power efficiency but at the cost of an extra dedicated inductor and thus larger die. Also, it uses a 2.5-V supply, thus making it unrealistic in today’s scaled CMOS. From the FoM point of view, the class-C oscillator [9] exhibits a better performance than the class-F3 oscillator. However, the voltage swing constraint in class-C limits its phase noise performance. As can be seen, the class-F3 demonstrates more than 6 dB better phase noise with almost the same supply voltage. Consequently, the class-F3 oscillator has reached the best phase noise performance with the highest power efficiency at low voltage supply without the die area penalty of the noise-filtering technique or voltage swing constraint of the class-C VCOs. Class-F3 operation is also extended to mm-wave frequency generation in [32] and [33] which may interest a curious reader. Table Comparison with relevant oscillators

	This work	[9]	[8]	[29]	[10]	[30]	[2]	[20]
Technology	CMOS 65 nm	CMOS 130 nm	CMOS 350 μm	CMOS 65 nm	CMOS 55 nm	BiCMOS 0.130 μm	CMOS 90 nm	CMOS 65 nm
Supply voltage (V)	1.25	1	2.5	1.2	1.5	3.3	1.4	0.6
Frequency (GHz)	3.71	5.2	1.2	3.921	3.351	1.56	0.915	3.7
Tuning range (%)	25	14	18	10.2	31.4	9.6	24.3	77
PN at 3MHz (dBc/Hz)	−142.2	−141.2	−152	−141.7	−142	−150.4	−149	−137.1
Norm. PN2 (dBc/Hz)	−154.3	−147.5	−154.8	−154.4	−153.3	−155	−149	−149.21
IDC (mA)	12	1.4	3.74	18	12	88	18	17.5
Power consumption (mW)	15	1.4	9.25	25.2	27	290	25.2	10.5
FoM3 (dB)	192.2	195	195	189.9	189	180	184.6	188.7
	200.2	198.4	200.7	190	199	179.7	192.3	206.5
Inductor/transformer count	1	1	2	2	1	1	1	1
Area (mm2)	0.14	0.11	N/A	0.19	0.196	N/A	N/A	0.294
Oscillator structure	Class-F3	Class-C	Noise filtering	Clip-and-restore	Class B/C	Colpitts	Traditional	Dual mode

1 After on-chip ÷2 divider. 2Phase noise at 3-MHz offset frequency normalized to 915-MHz carrier. 3FOM = |PN| + 20 log10((f0/Δf)) − 10 log10(PDC/1mW). 4FOMT = |PN| + 20 log10((f0/Δf)(TR/10)) − 10log10(PDC/1mW).

We showed a LC-tank oscillator structure that introduces an impedance peak around the third harmonic of the oscillating waveform such that the third harmonic of the active device current converts into voltage and, together with the fundamental component, creates a pseudo-square oscillation voltage. The additional peak of the tank impedance is realized with a transformer-based resonator. As a result, the oscillator impulse sensitivity function reduces, thus lowering the conversion sensitivity of phase noise to various noise sources, whose mechanisms are analyzed in depth. Chief of these mechanisms arises when the active gm-devices periodically enter the triode region during which the LC tank is heavily loaded while its equivalent quality factor is significantly reduced. The voltage gain, relative pole position, impedance magnitude, and equivalent quality factor of the transformer-based resonator are quantified at its two resonant frequencies. The gained insight reveals that the secondary to the primary voltage gain of the transformer can be even larger than its turns ratio. A comprehensive study of circuit-to-phase-noise conversion mechanisms of different oscillators’ structures shows that the introduced class-F3 exhibits the lowest phase noise at the same tank’s quality factor and supply voltage. Based on this analysis, a class-F3 oscillator was prototyped in a 65-nm CMOS technology. The measurement results proved expected performance of this oscillator in silicon.

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In this chapter, we discuss and analyze a class of operation of an RF oscillator that further minimizes its phase noise. The main idea is to enforce a clipped voltage waveform around the LC tank by increasing the second harmonic of fundamental oscillation voltage through an additional impedance peak, thus giving rise to a class-F2 operation. As a result, the noise contribution of the tail current transistor on the total phase noise can be significantly decreased without sacrificing the oscillator’s voltage and current efficiencies. Furthermore, its special impulse sensitivity function (ISF) reduces the phase sensitivity to thermal circuit noise. The prototype of the class-F2 oscillator is implemented in standard TSMC 65 nm CMOS occupying 0.2 mm2. It draws 32–38 mA from 1.3-V supply. Its tuning range is 19% covering 7.2–8.8 GHz. It exhibits phase noise of −139 dBc/Hz at 3-MHz offset from 8.7-GHz carrier, translated to an average figure of merit of 191 dBc/Hz with less than 2-dB variation across the tuning range.

Spectral purity of RF LC-tank oscillators is typically addressed by improving a quality factor (Q) of its tank, lowering its noise factor (NF) and increasing its power consumption. Even though technology scaling increases the effective capacitance ratio, Cmax/min, of switchable tuning capacitors and, consequently, the oscillator tuning range, it does not improve the oscillator’s spectral purity parameters, such as tank Q-factor and oscillator NF. In fact, the tank Q-factor is slightly degraded in more advanced technologies mainly due to closer separation between the top metal and lossy substrate as well as thinner lower-level metals that are used in metal-oxide-metal (MoM) capacitors. On the other hand, transistor noise factor keeps on degrading in more advanced technologies. Consequently, NF increases and thus penalizes the oscillator phase noise (PN). Consequently, the oscillators of excellent spectral purity and power efficiency are becoming more and more challenging as compared to other RF circuitry that is actually gaining from the technology scaling. This has motivated an intensive research leading to new oscillator topologies [1–11]. In this chapter, we specifically address the ultra-low phase noise design space while maintaining high power efficiency. We describe a soft-clipping class-F2 oscillator topology based on enforcing a clipped voltage waveform around the LC tank by increasing the second-harmonic of the fundamental oscillation voltage through an additional impedance peak [8–10]. This structure shifts the oscillation voltage level so that it provides enough headroom for the tail current without compromising the oscillating amplitude. Consequently, the phase noise contribution of the tail current transistor is effectively reduced while maintaining the oscillator voltage efficiency. Furthermore, the class-F2 operation clips the oscillation waveform for almost half of the period, thus benefiting from the lower circuit-to-phase-noise conversion during this time span. The chapter is organized as follows: the trade-offs between the RF oscillator PN and power consumption are investigated in Section 4.2. Section 4.3 establishes the environment to introduce the class-F2 operation, its benefits, and constraints. The circuit-to-PN conversion mechanisms are studied in Section 4.4. Section 4.5 presents extensive experimental results.

The phase noise (PN) of the traditional oscillator (i.e., class-B) with an ideal current source at an offset frequency Δω from its fundamental frequency ω0 could be expressed as where Qt is the tank quality factor; αI is the current efficiency, defined as the ratio of the fundamental current harmonic Iω0 over the oscillator DC current IDC; and αV is the voltage efficiency, defined as the ratio of the oscillation amplitude Vosc (single-ended) over the supply voltage VDD. The oscillator power consumption is where Rin is an equivalent input parallel resistance of the tank modeling its losses. Equation (4.1) clearly demonstrates a trade-off between power consumption and PN. To improve the oscillator PN, one must increase PDC by scaling down Rin. This could be done by lowering the tank inductance while maintaining the optimal Qt. For example, by keeping on reducing the inductance by half, Rin could theoretically decrease by half at the constant Qt, which would improve phase noise by 3 dB with twice the power consumption at the same FoM.FoM = |PN| + 20 log10(ω0/Δω) − 10 log10(PDC/1mW). However, at some point, the resistance of the tank’s interconnections will start dominating the resonator losses and, consequently, the equivalent tank’s Q will start decreasing. Hence, the PN-versus-power trade-off will no longer be beneficial since the FoM will drop dramatically due to the Q-factor degradation. Coupling N oscillators is an alternative way of trading off the power for PN since it avoids scaling the inductance down to impractically small values. It can theoretically improve PN by a factor of N compared to a single oscillator [12, 13]. Unfortunately, the oscillator size increases linearly, i.e., 4× larger area for just 6 dB of PN improvement. In this chapter, we explain how to improve phase noise by utilizing two 1:n transformers that are connected back-to-back [8], as shown in Figure 4.1(b, c). The equivalent Rin and, thus, the oscillator PN are scaled down by a factor of ∼(1 + n2) without sacrificing tank’s Q-factor. Hence, PN improvement can potentially be much better than with the coupled oscillators (e.g., Figure 4.1(a)) at the same die area. In addition, the C2 and C3 tuning capacitors, which are not directly connected to the primary of the first transformer, appear at the input of the transformer network via the scaling factor of n2 and n4 as can be realized from Figure 4.1(c). This impedance transformation results in a significant reduction in the required value of all the capacitors (i.e., ∑i Ci), which reduces the routing parasitics (both inductive and capacitive), and improves the tuning range and PN of the oscillator. Even though by increasing the transformer’s turns ratio the tank input impedance will be reduced, the transformer Q-factor will not stay at the optimum level and will start dropping at some point [14]. It turns out that the turns ratio of n = 2 can satisfy the aforementioned constraints altogether. Figure Phase noise reduction techniques without sacrificing tank’s Q-factor: (a) coupled oscillators, (b) connecting two step-up transformers back-to-back, and (c) its equivalent circuit model. To sustain the oscillation of this differential tank, two transistors shall be added. Figure 4.2 illustrates the preliminary schematic and waveforms. Unfortunately, as gathered from Figure 4.3, this structure suffers the same issues as the traditional class-B oscillator when the ideal current source is replaced with a tail bias transistor, MT. The PN is ideally improved by 20 dB/dec through increasing the oscillation amplitude, provided the gm-devices M1,2 operate in saturation over the entire period. However, the slope of PN improvement deviates from the ideal case when M1,2 enter the triode region for a part of the oscillation period [15]. This problem is intensified especially when the oscillator operates at higher frequencies and larger IDC (i.e., ≥10 mA) is needed to satisfy the stringent spectral purity of the GSM standard [16]. Actually, the combination of the parasitic drain capacitance of the large-size MT with the entering the triode region by M1,2, cyclically short-circuits the tank, thus degrading its equivalent Q-factor and oscillator PN [17]. Furthermore, the oscillation voltage should provide minimum VDSAT across MT throughout the entire period to keep it in saturation. Consequently, αV becomes substantially less than 1, which translates to a significant PN penalty as clearly seen from (4.1). Larger MT needs lower VDSAT, which would increase αV. However, the tail transistor’s effective thermal noise will increase significantly for the same IDC [18]. As a consequence, the contribution of MT to the PN could be larger than that of gm-devices, which translates to a significant increase of the oscillator NF and thus its PN [16]. In addition, the MT parasitic capacitance, CT, will also increase with the side effect of a stronger tank loading. On the other hand, the combination of the sinusoidal drain voltage, large CT, and the entering of triode region by M1,2 will result in a dimple in the squarish shape of active device drain current (see Figure 4.2) with a 10%–20% reduction in αI and thus FoM of the oscillator [1, 16]. All the above reasons contribute to reducing the rate of PN improvement versus Vosc to about 10 dB/dec when M1,2 enter the triode region for a part of the oscillation period. Hence, a huge 8-dB PN difference in Figure 4.3 is observed between the ideal and real operation of the oscillator. Consequently, the novel oscillator must not be sensitive to the excess gm-device noise in the triode intervals. It should also break the trade-off between αV and NF. Figure Preliminary oscillator schematic and its simulated voltage and estimated current waveforms at f0 = 8 GHz, VDD = 1.2 V, IDC = 33 mA, Leq = 80 pH, and Ceq = 4.95 pF. Figure Simulated phase noise performance of the preliminary oscillator of Figure 4.2 versus gate differential oscillation voltage for the ideal and real current sources.

Before introducing a new phase noise (PN) reduction technique, let us take a closer look at the harmonic component of the drain current ID of the M1 and M2 gm-devices in Figure 4.2. Ideally, ID is a square wave containing fundamental and odd harmonics. The odd harmonics through M1 and M2 are 180° mutually out-of-phase and appear as differential-mode (DM) input signals for the tank. The ID also contains even harmonics due to the large oscillation voltage, non linearity of M1,2, and large parasitic capacitance of MT. However, the even harmonics through M1 and M2 are mutually in-phase with ±90° phase shift to their related odd harmonics, as shown in Figure 4.4. Consequently, these even harmonics appear as a common-mode (CM) input for the tank. The conventional tank input impedance has only one peak at the fundamental frequency ω0. Therefore, the tank filters out the drain current harmonics and ultimately a sinusoidal voltage is seen across the tank. Now, suppose the tank offers an additional CM input impedance peak around the second harmonic (see Figure 4.5). Then, the second harmonic of ID is multiplied by the tank’s CM input impedance to produce a sinusoidal voltage at 2ω0 that is in quadrature to the fundamental oscillation voltage produced by the tank’s DM impedance at ω0. The combination of both waveforms creates the desired oscillation voltage around the tank, as shown in Figure 4.5, thus justifying the class-F2 designation. Figure Drain current of M1,2 devices of Figure 4.2 in time and frequency domains. Figure New oscillator’s waveforms in time and frequency domains. ζV is defined as the ratio of the second-to-first harmonic components of the oscillation voltage. where Rin and Rcm are, respectively, the tank DM and CM impedance magnitude at ω0 and 2ω0. Figure 4.6 illustrates the oscillation voltage and its related impulse sensitivity function (ISF) based on Equation (38) in [21] for different ζV values. Clearly, ζV should be 0.3 to have the widest flat span in the tank’s oscillation voltage. The is 0.35 for ζV = 0.3 compared to 0.5 for the traditional oscillator, which leads to a 1.5-dB PN and FoM improvements. Furthermore, ISF is negligible when the gm-devices work in the triode region and inject the most thermal noise into the tank. Consequently, the oscillator FoM improvement should be larger than that predicted by just the ISFrms reduction. More benefits of the class-F2 operation will be revealed in the following sections. Figure Effect of adding second harmonic in the oscillation voltage waveform (top) and its expected ISF based on Equation (38) in [21] (bottom). The argument related to Figure 4.5 suggests the creation of an additional CM input impedance peak at the second harmonic of main differential resonance. Incidentally, the introduced step-up 1:2 transformer acts differently to the CM and DM input signals. Figure 4.7(a) illustrates the induced current at the transformer’s secondary when the primary winding is excited by a differential signal. All induced currents circulate in the same direction at the transformer’s secondary to satisfy Lenz’s Law. Consequently, the induced currents add constructively, which leads to a strong inter-winding coupling factor (km ≥ 0.7). However, when the transformer’s primary is excited by a CM signal (Figure 4.7(b)), the induced currents at the right-hand and left-hand halves of the transformer’s secondary winding circulate in opposite directions, thus largely canceling each other. The residual current results in a very small km ≤ 0.2 for the CM excitation. Consequently, the concept of using two modes of a transformer for waveform shaping (proposed in [19] for a power amplifier) will be adopted here to realize the special tank input impedance of Figure 4.5. Note that an equivalent lumped-element model in [14, 20] cannot simultaneously cover both CM and DM types of behavior, and would produce wrong results. Hence, we suggest to utilize the transformer’s S-parameters and PSS analysis to simulate the novel class-F2 oscillator. Figure Transformer behavior in (a) differential-mode and (b) common-mode excitations. Figure New transformer-based resonator: (a) schematic, (b) its simplified equivalent differential-mode circuit (km(DM) ≈ 1), and (c) simplified tank schematic for common-mode input signals (km(CM) ≈ 0). Figure 4.8 shows the newly invented tank of a class-F2 oscillator. The C1d and C3 are intentionally chosen as fixed capacitors while the DM and CM resonant frequencies are tuned by C1c (fine) and C2 (coarse). The DM main resonant frequency is The inductance reduction and capacitance multiplication factors of the dual-transformer tank are directly contained in (4.5). The CM input signal can neither see the second transformer nor C2 and C3 due to negligible km(CM). In addition, differential capacitors also act as open circuit for the CM signals. Consequently, the tank’s CM resonant frequency is There is no tank impedance scaling for the CM excitation. Hence, the CM input impedance peak should be higher than the DM peak, as clearly seen from Figure 4.9 (top). To operate properly, CM-to-DM resonance ratio must be adjusted to 2: As a consequence, the frequency tuning requires a bit different consideration than in the class-B oscillators. Both C1c and C2 must, at least at the coarse level, be changed simultaneously to satisfy (4.7) such that f1c coincides with 2f1d. This adjustment is entirely a function of the ratio of the tuning capacitors, which is precise, thus making ζf largely independent from process, voltage, and temperature (PVT) variations. Let us now consider the required accuracy of this ratio ζf. The transformer and switching capacitors are designed based on maximum Q-factor at the operating frequency f1d. The tank Q-factor drops at least 3× at f1c = 2f1d. Consequently, the tank CM impedance bandwidth is very wide, as seen in Figure 4.9. Therefore, the oscillator is less sensitive to the position of f1c and thus the tuning capacitance ratio. A realistic 5% error in ζf has no significant adverse effects on the oscillator waveform and thus its PN. The schematic and waveforms of the new oscillator are shown in Figures 4.10 and 4.11. Even though the second harmonic injection reduces the drain oscillation voltage by V0 during the negative clipping interval, it increases its positive peak by V0 (see Figure 4.6(a)). It means the drain oscillation span is shifted from 0-to-2VDD in the traditional oscillator to V0-to-(2VDD + V0) in the class-F2 operation. Hence, the larger current source voltage headroom and lower noise factor are achieved without compromising the oscillation amplitude. Furthermore, the V0 headroom also reduces the dimple in the core-device drain current (compare Figures 4.2 and 4.11), which helps the class-F2 current efficiency to be closer to the ideal value of 2/π. Figure Simulated characteristics of the transformer-based tank of Figure 4.8: (top) magnitude of input impedance Zin; (bottom) tank voltage gain between gate and drain of core devices. Figure Transformer-based class-F2 oscillator schematic. Figure Simulated oscillation waveforms of the class-F2 oscillator at VDD = 1.2 V and IDC = 29 mA: (top) oscillation voltage of different circuit nodes and (bottom) core transistors drain current. Figure 4.9 illustrates the tank CM/DM input impedance and passive voltage gain between the gate and drain of M1,2 versus frequency. Unfortunately, the tank exhibits two other undesired DM resonant frequencies (f2d, f3d) due to imperfect km of the two transformers that create two leakage inductances [14]. Consequently, the circuit loop must guarantee the oscillation only at the desired DM resonance, f1d. Although CM demonstrates much larger input impedance peak, the two transformers effectively reject (attenuate by >40 dB) the CM signals. The root-locus plot in Figure 4.12 illustrates the DM pole movements toward zeros for different oscillator loop transconductance gains GM. The first and third frequency conjugate pole pairs (ω1d, ω3d) move into the right-hand plane by increasing the absolute value of GM, while the second conjugate pole ω2d is pushed far away from the imaginary axis. This guarantees that the oscillation will not happen at ω2d. Furthermore, it can be shown that ω3d poles move to much higher frequencies with much lower input impedance peak and tank voltage gain if enough differential capacitance is located at T1 primary windings. It justifies the existence of the non-switchable differential capacitor C1d. Consequently, the loop gain will not be enough to satisfy the Barkhausen criterion for ω3d. Figure Root-locus plot of the class-F2 oscillator.

According to the linear time-variant (LTV) model [21], the phase noise of an oscillator at an offset frequency Δω from its fundamental frequency ω0 is expressed as where qmax = Ceq·Vosc is the maximum charge displacement across the tuning capacitors and Vosc = αI·Rin·IDC is the single-ended oscillation amplitude at the drain of gm-devices. The NL,i in (4.8) is the effective noise power produced by ith device given by where is the white noise current density of the ith noise source and Γi is its corresponding ISF function. Obtaining the ISF of various oscillator nodes is the first step in calculating the oscillator’s PN. The ISF functions are simulated by injecting a 20 femto-coulomb charge (Δq) throughout the oscillation period and measuring the resulting time shifts, Δti. Figure 4.13(a) illustrates the ISF of various tank nodes. The soft clipping reduces by 30% the effect of losses on the oscillator PN due to single-ended switchable C1cThe single-ended switchable capacitor is used to adjust the CM resonant frequency. However, its Q-factor is almost half of that of the differential structure for the same Cmax/Cmin. The soft clipping largely compensates the effect of additional losses due to its lower Γrms value. and T1 primary windings. However, ISF functions of the T1 secondary and T2 primary/secondary winding noise sources (including C2 and C3) are not improved due to the sinusoidal (i.e., conventional) waveforms at IMA,B and GA,B nodes. Figure 4.13(a) indicates that Ga,b are the most sensitive nodes. Hence, C3 is constructed as a fixed MoM capacitor and the transformer was designed with a goal of maximizing Q-factor of the secondary winding. To calculate a closed-form PN equation, the oscillator model is simplified in Figure 4.14. The GDS1,2(t) represent the channel conductance of M1,2. The GM1,2(t) and GMT(t) model the transconductance gain of M1,2 and MT, respectively. The original tank is pruned to a parallel Leq, Ceq, Rin with noiseless voltage gain of G0 (see Figure 4.8(b)). The simplified tank’s equivalent ISF can be roughly estimated by an average of the tank’s contributing ISF functions of Figure 4.13(a) and is shown in Figure 4.13(b) as green curve. The effective noise power of the tank is illustrated in Figure 4.13(c) as green curve and its average power is approximated by Consequently, the soft clipping reduces NTank by 20% compared to the traditional oscillator. Figure Mechanisms of circuit-to-phase-noise conversion across the oscillation period in the class-F2 oscillator: (a) simulated ISF of different tank nodes, (b) equivalent ISF in the simplified oscillator schematic of Figure 4.14, (c) simulated effective power spectral density of the oscillator’s noise sources normalized to KT/Rin, (d) oscillation waveforms and operation region of M1,2, (e) transconductance and channel conductance of M1, (f) loaded Q-factor and effective parallel input resistance of the tank, (g) power spectral density of M1 noise sources normalized to 4KT/Rin, (h) simulated ISF function of M1 channel noise, and (i) simulated effective power spectral density of different noise sources of M1 normalized to KT/Rin. Figure Simplified noise source model of the class-F2 oscillator. The effects of noise on the oscillator PN due to channel conductance (GDS) and transconductance gain (GM) of M1,2 transistors are separately investigated. Figure 4.13(d) illustrates various operational regions of M1,2 across the oscillation period. When M1,2 are not turned off, they work mainly in the deep triode region where they exhibit a few ohms of channel resistance, as indicated in Figure 4.13(e). Consequently, the combination of the large parasitic capacitance of MT with low channel resistance of M1,2 in this deep triode region makes a low impedance path between the tank and ground. The literature interprets this as the tank loading event and defines implicit parameters such as effective tank Q-factor (Qeff) and input parallel resistance (Rineff) to justify the oscillator phase noise degradation due to this phenomenon. As shown in Figure 4.13(f), the tank Qeff and Rineff drop 4–5× when M1,2 operate in the deep triode. These “effective” parameters merely indicate that more noise is injected then into the tank. However, they do not ordain how much of that circuit noise converts to phase noise, especially when the drain oscillation wave is not conventionally sinusoidal. The proper approach should be based on the channel conductance noise power and its related ISF If we had an ideal current source, M1,2 noise would be injected to the tank only during the commutating time (hachure areas in Figure 4.13(e-g)). At the remaining part of oscillation period, one transistor is off and the other one is degenerated by the ideal current source and thus noiseless. However, the output impedance of a practical current source is low for such a high IDC = 30 mA and f0 = 8 GHz. Consequently, M1,2 can inject significant amount of noise to the tank when they operate in deep triode region outside the commutating time (i.e., gray area in Figure 4.13(g)). Note that gm-devices generate ∼7× higher amount of noise compared to the tank loss in the gray area, which can potentially increase the phase noise of the oscillator. However, the ISF of channel noise of M1,2 is very small in that time span as shown in Figure 4.13(h). Hence, the excessive transistor channel noise (or excessive loaded tank noise of the conventional approach) cannot convert to phase noise. Consequently, the effective noise power of the gm-device channel conductance is negligible, as illustrated in Figure 4.13(i), and its average power is approximated by Note that NGDS is at least 4× larger for the traditional oscillator, especially when a large αV is needed [22]. Figure 4.13(e) shows M1 transconductance gain GM1 across the oscillation period. To sustain the oscillation, the combination of the transformers’ passive voltage gain (G0) and effective negative transconductance of the gm-devices needs to overcome the tank and M1,2 channel resistance losses. Consequently, where GDS1EF describes the effective value of the instantaneous conductance GDS1(t) of M1,2 [22]. It can be shown that GDS1EF could be as large as 1/Rin when the oscillator is biased near the voltage limited region [1]. Therefore, the effective noise due to GM of core transistors can be calculated by Equation (4.14) indicates that the second harmonic injection (i.e., class-F2 operation) demonstrates no benefit for NGM, but the transformers’ voltage gain still offers significant benefits. To estimate the PN contribution of MT, its transconductance should be calculated first. where VT is the overdrive voltage of MT equal to the drain–source voltage. The clipping voltage level is By dedicating a half of V0 headroom to MT, By substituting IDC with Vosc/(αIRin) in (4.17), As discussed earlier, αI and αV could be as large as 0.6 and 0.9 in this oscillator, and optimum ζV is about 0.3. Hence, (4.18) is simplified to GMT ∼ 15/Rin. As revealed by Figure 4.13(b, orange), ΓMT,rms is only 0.08 due to relatively large VT of the class-F2 operation. Consequently, The contribution of MT to the PN is less than that of the tank and is about 20% of the total. This share could easily be higher than 50% for the traditional oscillator at the same αV and IDC as discussed in [16, 17]. Finally, the total oscillator effective noise power (NT) and noise factor (NFTotal) are given by Equation (4.20) indicates that the effective noise factor of the class-F2 oscillator is very close to the ideal value of (1+γ) despite the aforementioned practical issues. The phase noise can easily be calculated by replacing (4.20) in (4.8). The oscillator FoM normalizes the PN performance to ω0 and PDC, yielding Table 4.1 verifies the solidity of the presented phase noise analysis by comparing the results of SpectreRFTM PSS, Pnoise simulations with the derived theoretical equations. The expressions estimate the oscillator PN and share of different noise sources with an acceptable accuracy. It is also instructive to compare in Table 4.2 the benefits and drawbacks of the two flavors of class-F operation. Intuitively, the third-harmonic injection in class-F3 (Chapter 3) demonstrates a pseudo-square waveform with smaller ISFrms value and shorter commutating time. Consequently, it offers lower NFTank and NFGM. On the other hand, class-F2 operation provides larger voltage overhead for the gm-devices and tail current transistor without sacrificing the oscillator αV. Hence, it exhibits better NFMT, NFGDS, and αV. As expected, the effective noise factor and FoM of both topologies turns out to be identical. However, this implementation of class-F2 automatically scales down the tank input parallel resistance and thus offers lower PN at price of larger area and slightly lower Q-factor due to the interconnection of the two transformers. Table Comparison between the results of SpectreRF PSS, Pnoise simulation and theoretical equations at 8-GHz carrier for VDD = 1.2 V, Rin = 60 Ω, Leq = 80 pH, γMT = 1.3, and γM1,2 = 1

	Theoretical Equations		SpectreRF Simulation
	Value	Share	Value	Share
NTank	5.50·10−23 V2/Hz	31%	4.71·10−23 V2/Hz	28.4%
NM1,2 = NGDS + NGMT	8.63·10−23 V2/Hz	48.8%	8.78·10−23 V2/Hz	53%
NMT	3.59·10−23 V2/Hz	20.2%	3.08·10−23 V2/Hz	18.6%
NT = NTank + NM1,2 + NMT	17.72 · 10−23 V2/Hz	100%	16.57 · 10−23 V2/Hz	100%
qmax (coulumbs)	5.34 · 10−12		5.34 · 10−12
Phase noise@10MHz	−151 dBc/Hz		−151.33 dBc/Hz

Table Comparison between two flavors of class-F oscillator for the same carrier frequency = 8 GHz, VDD = 1.2 V, tank Q-factor = 14, Δf = 10 MHz, and RP = 240 Ω

	Expression	Class-F3	Class-F2
αI	Iω0 / IDC	0.6	0.6
αV	Vosc/VDD	0.8	0.9 (✓)
NFTank	NTank/(KT/Rin)	0.7 (✓)	0.8
NFGDS	NGDS/(KT/Rin)	0.3	0.25 (✓)
NFGM	NGM/(KT/Rin)	≈ 0.7γM1 (✓)	≈ γM1
NFGMT	NGMT/(KT/Rin)	≈ 0.5γMT	≈ 0.4γMT (✓)
NFTotal		3.7dB (✓)	4.1dB
FoM		192.9dB (✓)	192.9dB (✓)
Rin		≈ Rp = 240Ω	≈ Rp/(1 + n2) = 60Ω (✓)
PDC		8mW	36mW
Phase noise		−144 dBc/Hz	−150.5 dBc/Hz (✓)

This oscillator targets GSM-900 MHz and DSC-1800 MHz base-station PN requirements. Electromagnetic (EM) simulations reveal that the tank Q-factor would be slightly (i.e., ∼10%) better at 8 GHz as compared to 4 GHz for the same Rin and tuning range. However, the 1/f noise upconversion would be more severe at 8 GHz due to a larger share of the non linear Cgs of gm-devices to the total tank’s capacitance. Furthermore, the output impedance of the current source is lower at higher frequencies, which would lead to higher PN penalty due to the tank loading. Consequently, there seems to be altogether no clear performance advantage of the 8 GHz over 4 GHz operation. Considering the fact that this oscillator has two transformers, the 8 GHz center frequency was chosen mainly to save die area. Figure Die photograph of the class-F2 oscillator. The class-F2 oscillator, whose schematic was shown in Figure 4.10, was realized in TSMC 1P7M 65 nm CMOS process technology. The die photograph is shown in Figure 4.15. The oscillator core die area is 0.2 mm2. The differential transistors are thick-oxide devices of 22(4 μm/0.28 μm) dimension. However, the tail current source MT is implemented as a standard 1 mm/0.24 μm thin-oxide (tox = 2.6 nm) device. Note that the thin-oxide device produces lower 1/f noise corner than the thick one at the same area [23]. The aluminum capping layer (1.45 μm), which is intended to cover bond pads, is strapped to the ultra-thick top copper layer (3.4 μm) to form the windings and improve the transformer’s primary and secondary Q-factor to 14 and 20, respectively, at 8 GHz. The transformer’s primary and secondary differential self-inductance is 560 and 1650 pH, respectively, with the DM and CM magnetic coupling factors of 0.8 and 0.15, respectively. Four differential switched MOM capacitors BC0−BC3 with the resolution of 40 fF placed across T1 secondary realize coarse tuning bits (C2), while the fine control bits BF0−BF2 with LSB of 20 fF adjust ωc to near 2ω1d to satisfy (4.7) and thus the class-F2 operation. The effective Cmax/Cmin of the switched capacitor structures is determined by the strong trade-off between the oscillator tuning range (TR) and tank Q-factor degradation due to the switch series resistance. The switched-capacitor’s Q-factor is about 45 for 25% TR at 8 GHz. Furthermore, the interconnections of the two transformers also increase the tank losses by 10%, resulting in an average Q-factor of 14 for the entire tank. The supply voltage connects to the center tap of T1 primary along with a 100 pF on-chip decoupling capacitor. The center tap of T2 secondary is connected to the bias voltage VB, which is fixed at VDD to minimize the number of supply domains and to guarantee safe oscillator start-up. The oscillator is very sensitive to noise at the M1,2 gates (see Figure 4.13(a)). Fortunately, no DC current is drawn from VB, so an RC filter of slow time constant is placed between VDD and VB to further reduce the bias voltage noise. Both T1 secondary and T2 primary winding center taps are connected to ground to avoid any floating nodes and make a return path for the negligible second-harmonic current to improve the waveform symmetry. The measured and simulated PN at 4.35 GHz (after the on-chip ÷2 divider) at 1.3 V and 32 mA current consumption are shown in Figure 4.16. The PN of −145 dBc/Hz at 3 MHz offset lies on the 20 dB/dec region, which extrapolates to −174.7 dBc/Hz at 20 MHz offset (normalized to 915 MHz) and meets the GSM TX mobile station (MS) requirements with a very wide 13 dB margin. The GSM/DCS “micro” base-station (BTS) and DCS “normal” BTS specs are met with a few dB of margin. These PN numbers are the best ever published at low VDD (i.e., ≤1.5 V). However, the toughest GSM base-station “normal” specifications at 800-to-900 kHz offset are within 1 dB of reach. The measured PN is just 1 dB higher than simulation in the 20-dB/dec region due to the power supply noise and additional tank loss caused by the routing of the tuning capacitors and dummy fill metals around the transformer. Figure Measured (blue) and simulated (red) phase noise plots at 4.35 GHz, VDD = 1.3 V and PDC = 41 mW. Specifications (MS: mobile station, BTS: basestation) are normalized to the carrier frequency. The measured 1/f3 PN corner shows less than 100 kHz increase over the simulation and is ∼350 and ∼250 kHz at the highest and lowest side of the tuning range, respectively. This excellent 1/f3 performance is achieved, thanks to the following reasons: first, the 1/f noise of the tail current source can appear as a CM signal at T1 primary and modulate the oscillation voltage. However, the T1 transformer will effectively filter out this CM AM signal, thus preventing any AM-to-PM conversion at the C2 switched capacitors and nonlinear Cgs of gm-devices. Second, the class-F2 tank has two impedance peaks at the fundamental oscillation frequency and its second harmonic. Hence, the second harmonic of the drain current flows into a resistance of the tank instead of its capacitive part. It effectively reduces the 1/f noise upcon-version to the 1/f3 phase noise due to Groszkowski phenomenon [24]; we will discuss this phenomenon intensively in Chapter 5. Third, the soft clipping effectively reduces the voltage variation of VT, as shown in Figure 4.11. Intuitively, it could reduce the DC and even-order coefficients of ISF at this node and thus alleviate the 1/f noise conversion of the tail current transistor. The PN noise beyond the 10-MHz offset is dominated by thermal noise floor from the divider and buffer set at −162 dBc/Hz. The oscillator has a 19% tuning range from 7.2 to 8.7 GHz. Figure 4.17 shows the phase noise and FoM of the oscillator at 3-MHz offset across the tuning range (after the ÷2 divider). The average FoM is as high as 191 dBc/Hz and varies less than 2 dB. The oscillator also reveals a very low frequency pushing of 42 and 22 MHz/V at the highest and lowest frequencies, respectively. Figure 4.18 shows the PN performance versus its current consumption. The circuit cannot satisfy Barkhausen oscillation criterion at IDC < 7 mA. The oscillator phase noise is improved only by 10 dB/dec between 7 and 12 mA due to the drop in the oscillator current efficiency αI and loading of the tank’s Q-factor by the gm-devices entering the linear region. Note that even though the tank has an additional impedance at 2ω0, the second harmonic of the drain current is negligible and, consequently, the drain oscillation resembles a sinusoid. However, by further increasing the drain current, the soft clipping phenomenon appears where the tank loading and tail transistor noise effects are reduced significantly due to the class-F2 operation. Consequently, PN improves by almost 20 dB/dec, which demonstrates a few dB of improvement compared to the traditional class-B operation (compare Figures 4.3 and 4.18). Figure 4.18 also indicates that the circuit can sustain the oscillation even with 4× lower IDC and thus GMEF, which translates into sufficient margin for the oscillator start-up over PVT variations. Figure Measured phase noise and figure of merit (FoM) at 3 MHz offset versus carrier frequency. Figure Measured phase noise at 3 MHz offset frequency from 4.3 GHz carrier versus the oscillator current consumption. Table Comparison with relevant ultra-low phase noise oscillators

	This work	[13]	[27]	[1]	[17]	[25]	[26]
Technology	CMOS 65 nm	CMOS 65 nm	CMOS 65 nm	CMOS 65 nm	MOS 350 μm	CMOS 55 nm	BiCMOS 130 nm
Supply voltage (V)	1.3	2.15	1.5	1.25	2.5	1.5	3.3
Frequency (GHz)	4.351	4.07	3.921	3.71	1.2	3.351	1.56
Tuning range (%)	19	19	10.2	25	18	31.4	9.6
PN at 3 MHz (dBc/Hz)	−144.8	−146.7	−147.7	−142.2	−152	−142	−150.4
Norm. PN2 (dBc/Hz)	−158.3	−159.6	−157.2	−154.3	−154.8	−153.3	−155
Power consumption (mW)	41.6	126.8	48	15	9.25	27	290
FoM (dB)	191.83	188.3	190.1	192.2	195	189	180
FoMT4 (dB)	197.4	193.4	190.3	200.2	200.7	199	179.7
Transformers/inductors count	2	2	2	1	2	1	1
Oscillator structure	Class-F2	Dual core Class-C	Hard clipping	Class-F3	Noise filtering	Class-B/Class-C	Colpitts

1 After on-chip ÷2 divider. 2 At 3-MHz offset frequency normalized to 915-MHz carrier. 3FoM drops to 191.5 dB by considering the divider power consumption of 2.6 mW. 4FOMT = |PN| + 20 log10((f0/Δf) (TR/10)) - 10 log10(PDC/1mW). Table 4.3 summarizes the performance of the class-F2 oscillator and compares it with the best spectral purity relevant oscillators. Note that this oscillator demonstrates the best PN with the highest power efficiency at a relatively low supply voltage. Only the dual-core class-C oscillator [13] offers better PN performance but at the price of 1.65× larger VDD, 3× higher power consumption, and 3 dB lower FoM or power efficiency.

In this chapter, we have presented and analyzed a class-F2 oscillator where an auxiliary impedance peak is introduced around the second harmonic of the oscillating waveform. The second harmonic of the active device current converts into voltage and, together with the fundamental component, creates a soft clipped oscillation waveform. The class-F2 operation offers enough headroom for the low noise operation of the tail current transistor without compromising the oscillator current and voltage efficiencies. Furthermore, the special ISF of the soft clipping waveform reduces significantly the circuit-to-phase-noise conversion. The additional resonant frequency is realized by exploiting a different transformer behavior in common-mode and differential-mode excitations. In addition, the tank input impedance is also scaled down without sacrificing its Q-factor. Consequently, this structure is able to push the phase noise much lower than practically possible with the traditional LC oscillators while satisfying long-term reliability requirements.

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In this chapter, we introduce a method to reduce a flicker (1/f) noise upcon-version in voltage-biased RF oscillators. Excited by a harmonically rich tank current, a typical oscillation voltage waveform is observed to have asymmetric rise and fall times due to even-order current harmonics flowing into the capacitive part, as it presents the lowest impedance path. The asymmetric oscillation waveform results in an effective impulse sensitivity function (ISF) of a non-zero dc value, which facilitates the 1/f noise upconversion into the oscillator’s 1/f3 phase noise. We demonstrate that if the ω0 tank exhibits an auxiliary resonance at 2ω0, thereby forcing this current harmonic to flow into the equivalent resistance of the 2ω0 resonance, then the oscillation waveform would be symmetric and the flicker noise upconversion would be largely suppressed. The auxiliary resonance is realized at no extra silicon area in both inductor- and transformer-based tanks by exploiting different behavior of inductors and transformers in differential- and common-mode excitations. These tanks are ultimately employed in designing modified class-D and class-F oscillators in 40-nm CMOS technology. They exhibit an average flicker noise corner of less than 100 kHz.

Close-in spectra of RF oscillators are degraded by a flicker (1/f) noise upconversion. The resulting low-frequency phase noise (PN) fluctuations can be mitigated as long as they fall within a loop bandwidth of an enclosing phase-locked loop (PLL). However, the PLL loop bandwidths in cellular transceivers are less than a few tenths to a few hundreds of kHz [1,2], which is below the typical 1/f3 PN corner of CMOS oscillators [3–5]. Consequently, a considerable amount of the oscillator’s low frequency noise cannot be filtered by the loop and will adversely affect the transceiver operation. Figure Class-B oscillator: (a) with tail transistor MT; (b) with tail resistor RT; and their PN when (c) MT is always in saturation; (d) MT enters partially into triode. In a current-biased oscillator, flicker noise of a tail transistor, MT, modulates the oscillation voltage amplitude and then upconverts to PN via an AM–PM conversion mechanism through nonlinear parasitic capacitances of active devices, varactors, and switchable capacitors [6,7] (see Figure 5.1(a)).It is shown in [6] that for certain values of varactor bias voltages, this upconversion is almost eliminated. An intuitive solution is to configure the oscillator into a voltage-biased regime, which involves removing the MT [8] or replacing it with a tail resistor, RT, in Figure 5.1(b). Such expected reduction is highly dependent on the tail transistor’s operating region. If MT in Figure 5.1(a) is always in saturation, the amount of 1/f noise is considerable and the tail resistor RT in Figure 5.1(b) could improve the low-frequency PN performance, as shown in Figure 5.1(c). However, in advanced CMOS process nodes with a reduced supply voltage, MT partially enters the triode region, thereby degrading the oscillator’s effective noise factor but improving the 1/f noise upconversion; see Figure 5.1(d). In [3], class-C oscillators were designed with a tail transistor and a tail resistor. Measured 1/f3 corners are almost the same, thus supporting our discussion.The actual flicker noise reduction mechanism of class-C oscillators was revealed in [9]. However, regardless of the MT operating region, removing this source would still not completely eliminate the 1/f noise upconversion. Figure (a) Current harmonic paths; (b) drain current in time and frequency domains; (c) frequency drift due to Groszkowski effect. Another mechanism of the 1/f upconversion is due to Groszkowski effect [10]. In a harmonically rich tank current, the fundamental component, IH1, flows into the equivalent parallel resistance of the tank, Rp. Other components, however, mainly take the capacitive path due to their lower impedance; see Figure 5.2(a). In any balanced RF oscillating circuit, odd harmonics circulate in a differential path, while even harmonics flow in a common-mode path through the resonator capacitance and the switching transistors to ground [32]. Compared to the case with only the fundamental component, the capacitive reactive energy increases by the higher harmonics flowing into them. This phenomenon makes the tank’s reactive energy un-balanced. The oscillation frequency will shift down from the tank’s natural resonance frequency, ω0, in order to increase the inductive reactive energy and restore the energy equilibrium of the tank. This frequency shift is given by [11] where IHn is the nth harmonic component of the tank’s current. The literature suggests that this shift is static but any fluctuation in IHn/IH1 due to the 1/f noise modulates Δω and exhibits itself as 1/f3 PN [12]; see Figure 5.2(c). Although this mechanism has been known for quite some time, it is still not well understood how the flicker noise modifies the IHn/IH1 ratio. Furthermore, (5.1) suggests that all harmonics indiscriminately modulate the Groszkowski’s frequency shift by roughly the same amount, without regard to their odd/even-mode nature, which could be easily misinterpreted during the study of the flicker noise upconversion in cross-coupled oscillators. While recognizing the Groszkowski’s frequency shift as the dominant physical mechanism in voltage-biased oscillators, we turn our attention to the impulse sensitivity function (ISF) theory in researching the above questions. Hajimiri and Lee [13] have shown that upconversion of any flicker noise source depends on the dc value of the related effective ISF, which can be significantly reduced if the waveform has certain symmetry properties [13,14]. Another explanation was offered in [15,16] suggesting that if the 1/f noise current of a switching MOS transistor is to be modeled by a product of stationary noise and a periodic function w(t), then this noise can upconvert to PN if w(t) is asymmetric. In this chapter, we elaborate on a method proposed in [22, 23, 34] to effectively trap the second current harmonic into a resistive path of a tank in a voltage-biased oscillator topology. Doing so will reduce the core transistors’ low frequency noise upconversion by making the oscillation waveform symmetric and reducing the effective ISF dc value. We further investigate the effects of harmonics on the core transistors’ flicker noise upconversion by studying their impact on the oscillation waveform and on the effective impulse sensitivity function, Γeff,dc. It should be mentioned that several solutions are proposed in literature to reduce the 1/f noise upconversion due to Groszkowski’s frequency shift. The concept of a harmonically rich tank current degrading the close-in oscillator spectrum has been noticed for quite some time; however, the proposed solutions mostly include linearization of the system to reduce the level of current harmonics by limiting the oscillation amplitude by an AGC [17,18], or linearization of gm-devices [19,20], at the expense of the oscillator’s startup margin and increased 1/f2 PN. In a completely different strategy, a resistor is added in [21] in series with gm-device drains. An optimum value of the resistor minimizes the flicker noise upconversion; however, the 1/f noise improvement is at the expense of the 20-dB/dec degradation in oscillators with low VDD and high current consumption. The rest of this chapter is organized as follows. Section 5.2 shows how harmonic components of the drain current contribute to the flicker noise upconversion and shows how an auxiliary CM resonance at 2ω0 mitigates this upconversion. Section 5.3 demonstrates how the auxiliary resonance is realized and proves the effectiveness of the proposed method by implementing two classes of voltage-biased oscillators. Section 5.4 reveals the details of circuit implementations and measurement results.

Let us start by focusing on reducing the Groszkowski frequency shift. As shown in Figure 5.2(a), the oscillation frequency ωosc fluctuates around the tank’s natural resonant frequency ω0 due to the flow of higher harmonics of the current ID1,2 into the capacitive part of the tank. A voltage-biased class-B tank current in time and frequency domains is shown in Figure 5.2(b). Odd harmonics of the tank current are differential-mode (DM) signals; hence, they can flow into both differential- and single-ended capacitors. Even harmonics of the tank current, on the other hand, are common-mode (CM) signals and can only flow into single-ended (SE) capacitors. If the tank possesses further resonances coinciding with these higher harmonics (see Figure 5.3(a)), these components can find their respective resistive path to flow into, as shown in Figure 5.3(b). Consequently, the capacitive reactive energy would not be disturbed and the oscillation frequency shift Δω would be minimized (see Figure 5.3(c)). The input impedance Zin of such a tank is shown in Figure 5.3(d). The tank has the fundamental natural resonant frequency at ω0 and auxiliary CM and DM resonant frequencies at even- and odd-order harmonics, respectively. Minimizing the frequency shift Δω will weaken the underlying mechanism of the 1/f noise upconversion; however, realizing auxiliary resonances at higher harmonics has typically been area inefficient and can also degrade the PN performance. Consequently, the auxiliary resonance frequencies have to be chosen wisely. Figure (a) Auxiliary resonances at higher harmonics; (b) current harmonic paths; (c) frequency drift; (d) input impedance of the tank. Groszkowski frequency shift formula (5.1) indicates that all the contributing current harmonics IHn are weighted by almost the same coefficients. This means that, in practice, stronger current harmonics IHn contribute more to the frequency shift. Consequently, we can narrow down the required auxiliary resonances to these harmonics. On the other hand, ultimately, the low frequency noise upconversion depends on the oscillation waveform and the dc value of effective ISF. The various current harmonics contribute unevenly to the flicker noise upconversion since they result in different oscillation waveforms and effective ISF values. Investigating these differences reveals how many and at which frequencies the auxiliary resonances should be realized.

A (hypothetical) sinusoidal resonance tank current IH1(t) = |IH1| sin (ω0t) would result in a sinusoidal resonance oscillation voltage: VH1(t) = Rp1 · |IH1| sin (ω0t) = A1 sin (ω0t). Its ISF is also a zero-mean sinusoid but in quadrature with VH1(t) [24]. The flicker noise of core transistors (e.g., M1,2 in Figure 5.4(a)) in a cross-coupled oscillator is modeled by a current source between the source and drain terminals and exhibits a power spectral density as Figure Oscillator example: (a) schematic; (b) VDS, VGS, and gm of M1 transistor when oscillation voltage contains only fundamental component; (c) its ISF, NMF, and effective ISF. where K is a process-dependent constant, W and L are core transistors’ width and length, respectively, and Cox is an oxide capacitance per area. Due to the dependency of current noise on gm, the flicker noise source is a cyclostationary process and can be expressed as in which in,0(ω0t) shows the stochastic stationarity. α(ω0t) is the noise modulating function (NMF), which is normalized, deterministic, and periodic with maximum of 1. It describes the noise amplitude modulation; consequently, it should be derived from the cyclostationary noise characteristics [13]. In this case, an effective impulse sensitivity function is defined as Γeff(ω0t) = α(ω0t) · Γ(ω0t). M1,2 flicker noise cannot upconvert to PN if effective ISF has a zero dc value. Let us investigate the M1,2 flicker noise upconversion when the oscillation voltage ideally contains only the fundamental component. In Figure 5.4(a), VD1 = VDD − A1sin(ω0t), VG1 = VD2 = VDD + A1sin(ω0t). Assuming VDD = 1.2 V and A1 = 1 V, the gm of the M1 transistor under such VDS and VGS is found by simulations and is shown as dotted line in Figure 5.4(b). Under this condition, . ISF, NMF, and the effective ISF of the M1 flicker noise source are shown in Figure 5.4(c). The dc value of such an effective ISF is zero, resulting in no flicker noise upconversion. This is a well known conclusion and is referred to as a state where M1,2 transistors’ flicker noise cannot be upconverted to PN [16]. In reality, the tank current of voltage-biased oscillators is rich in harmonics. Due to physical circuit constraints, the even-order current harmonics lead by π/2, while the odd-order current harmonics are in-phase with the fundamental current IH1. The π/2 phase difference in even- and odd-order current harmonics considerably changes the oscillation waveform characteristics. For simplicity, we focus only on dominant harmonics, IH2 = |IH2| sin(2ω0t + π/2) and IH3 = |IH3| sin(3ω0t), as representatives of even- and odd-order current harmonics, respectively; however, the following discussion can be easily generalized for all harmonics. We also assume for now that the tank only contains SE capacitors. The differential current IH2 flows into the SE capacitors and creates a second-order voltage harmonic: where the −π/2 phase shift is due to the capacitive load. The oscillation voltage will then be VH1(t), VH2(t), and VT2(t) are plotted in Figure 5.5(a) for α2 = 0.1 and A1 = 1 V. VH1(t) has two zero-crossings within its period: at t1 and t2, their rise and fall times are symmetric with derivatives: . VH2’s zero-crossings are also at t1 and t2; however, . Consequently, the opposite slope polarities of VH1 and VH2 at t1 slow down the fall time of VT2, while the same slope polarities at t2 sharpen its rise time. Consequently, as can be gathered from Figure 5.5(a), VT2 features asymmetric rise and fall slopes. The resulting ISF of the gm transistor is calculated based on (36) in Ref. [13] and is shown in Figure 5.5(b), with its mean dependent on α2. Larger α2 leads to more asymmetry between VT2(t) rise and fall slopes; hence, Γeff,dc will increase. Furthermore, repeating the same simulations to obtain gm1 with drain and gate voltages that contain second harmonic components results in asymmetric gm1 and, consequently, NMF The slower rise/fall times increase the duration when M1 is turned on, thus widening gm1. A sharper rise/fall time decreases the amount of time when M1 is turned on, resulting in a narrower gm1. The NMF and effective ISF of such waveforms are shown in Figure 5.5(b). The effective ISF has a dc value which results in M1,2’s flicker to PN upconversion. Dependency of the dc value of the effective ISF on α2 is shown in Figure 5.5(c). Figure Conventional tank waveforms: (a) fundamental, VH1, second harmonic, VH2, voltage components, and oscillation waveform, VT2; (b) its ISF, NMF, and effective ISF; (c) Γeff,dc/Γeff,rms for different α2 values. This argument is valid for all even-order current harmonics, and we can conclude that the fluctuations in the even harmonics of the tank’s current convert to the 1/f3 PN noise through the modulation of the oscillating waveform. Let us now investigate a case of the tank current containing only odd-harmonic components, with IH3 = |IH3| sin(3ω0t) as a representative. IH3 flows mainly into the tank capacitors and creates a third harmonic voltage as Figure Conventional tank waveforms: (a) fundamental, VH1, third harmonic, VH3, voltage component, and oscillation waveform, VT3; (b) its ISF, NMF, and effective ISF. where, again, the −π/2 phase shift is due to the capacitive load. The oscillation voltage will then be VH1(t), VH3(t), and VT3(t) are plotted in Figure 5.6(d) for α3 = 0.1 and A1 = 1 V. It is obvious that the oscillation waveform falling and rising slopes are symmetric, and Γdc = 0, as easily gathered from Figure 5.6(e). The simulations show that gm1 is slightly asymmetric due to amplitude distortion of the oscillation voltage. However, this asymmetry is canceled out when multiplied by ISF (see Figure 5.6(e)), resulting in an effective ISF with almost zero dc value and thus preventing low-frequency noise upconversion. These arguments can be generalized for all odd-order harmonics. Consequently, the low-frequency noise of gm transistors does not upconvert to PN if the tank current only contains odd harmonics. Figure Ideal and real current waveforms. So far, we have assumed π/2 phase for IH2 and π phase for IH3; however, the exact phase shift between the fundamental and harmonic components depends on the transconductor nonlinearity. The ideal drain current in a class-B oscillator is a square wave. However, the core transistors enter triode region, resulting in the real current shape to exhibit a dimple. For this current waveform to appear, a current harmonic with twice the fundamental frequency and π/2 phase shift has to be added to the original waveform (which only contains odd harmonics), as shown in Figure 5.7. Hence, the phase delay of the second harmonic is not arbitrary but is constrained by the physical circuit. It is worth mentioning that in a class-C oscillator, where the transistors do not enter the triode region, the phase difference between the first and second harmonic is not π/2. The class-C oscillator shows less 1/f3 corner compared to the other topologies which is in agreement with our claim about the importance of the fundamental and second current phase shift on the low frequency noise upconversion. Let us investigate what happens to the voltage waveform and ISF if the fundamental and third-harmonic components are not in-phase, and have a phase shift of ϕ1. Following the same approach as in the manuscript and assuming A1 = 1, VH3 = α3 sin(3ω0t − π/2 + ϕ1). If for θ1 = ω0t1, VT = VH1 + VH3 = 0, then for θ2 = π + θ1, VT = sin(θ2) + α3 sin(3θ2 + ϕ1) = − sin(θ1) − α3 sin(3θ1 + ϕ1) = 0. Then the VT slopes at θ1 and θ2 would be Consequently, regardless of the exact phase difference between the current’s fundamental and third-harmonic components, the oscillation voltage in the presence of third (and, in general, odd) harmonics would have symmetric rise and fall times, and consequently they will not be responsible for 1/f to phase noise upconversion. Figure Tank’s current fundamental and second-harmonic phases in (a) class-D; (b) class-F3; and (c) class-C topologies. For the second-harmonic component, the story is entirely different. The most asymmetric rise and fall times of the oscillation voltage waveform happen when the fundamental and second-harmonic current components have exactly the π/2 phase difference. However, if the phase difference is not exactly π/2 (and it is, for example, π/2 − ϕ1), rise and fall times are still asymmetric and the ISF still contains a non-zero dc value. The proposed method would be still effective not at exactly ωCM = 2ω0, but at a CM resonance that has the ϕ1 − π/2 phase at 2ω0 and cancels out the extra phase difference, ϕ1, therefore, resulting in a completely symmetric rise and fall times. It is worth mentioning that if ϕ1 were originally close to π/2, the oscillation waveform should have theoretically very symmetric rise and fall times. However, due to the real-world circuit constraints, that situation could not be reproduced in simulations. Independent from the above explanations, we did some circuit-level simulations to show exact phase shift of the second harmonic compared to the fundamental components in class-D, class-F3, and also class-C topologies. The results are shown in Figure 5.8. For class-D and class-F3 topologies, the π/2 phase difference appears to be a very good estimation. However, as predicted for the class-C topology, π/2 phase difference is not a precise estimation. To further support that 1/f noise upconverts more to PN if α2 is increased, we tried to run some simulations on the voltage-biased class-B oscillator of Figure 5.9(a). Controlling the second-harmonic current is not very straightforward. It can be modified by changing the core transistors’ width, W, or by changing tank’s quality factor, Q. In both of these methods, the oscillation waveform amplitude would get affected. If we fix the oscillation amplitude when W or Q are swept, the second harmonic power modification range becomes very limited. On the other hand, by changing the transistors’ width, the flicker noise of the device also changes and adds another parameter. Consequently, in the following simulations, we swept the tank quality factor, and all the other parameters, such as transistor sizes, supply voltage, etc., are kept the same. With higher Q, the oscillation voltage increases, the device spends more time in triode region and becomes more non-linear, consequently generating more current harmonics. M1 and M2 in the class-B oscillator are thick-oxide 56μ/270n devices, VDD = 1.2V, RT = 9 Ohm. The capacitors are ideal and not tunable. The simulation results are shown in Figure 5.9(b). As we have discussed the flicker noise upconversion depends on the α2 value, which is proportional to the IH2/IHn ratio. Therefore, we reported the 1/f3 corner versus IH2/IHn, and it is obvious from Figure 5.9(b) that the corner increases for larger IH2/IHn ratios in this class-B oscillator. Figure (a) Voltage-biased class-B oscillator schematics; (b) 1/f3 corner versus IH2/IHn.

Thus far, we have shown that the even components of the tank’s current are chiefly accountable for the asymmetric oscillation waveform and the 1/f noise upconversion to PN. Let us investigate what happens to the oscillation waveform and effective ISF if the tank has an auxiliary CM resonance at 2ω0. Such resonance provides a resistive (i.e., via Rp2) path for IH2 to flow into it, and hence the voltage second-harmonic component is Figure Proposed tank waveforms: (a) fundamental voltage component, VH1; (b) voltage second harmonic in the presence of auxiliary resonance, VH2,aux; (c) oscillation waveform, VT2,aux; (d) its ISF, NMF, and effective ISF. The composite oscillation voltage will become VH1(t), VH2,aux(t), and VT2,aux(t) are plotted in Figure 5.10(a,b,c) for α2,aux = 0.1 and A1 = 1. The rise and fall times of the oscillation voltage are now symmetric (see Figure 5.10(c)) and so the ISF is zero mean, as shown in Figure 5.10(d). gm1, and thus NMF, are also completely symmetrical; consequently, the effective ISF has a zero dc value, preventing low-frequency noise from being upconverted. The oscillation waveform is still dependent on α2,aux, but the rise and fall times are always symmetric, thus keeping Γeff,dc zero. The second and third current harmonics are the most dominant in all classes of oscillators, so α2 and α3 are significantly larger than other αn for n = 4, 5,.... Meanwhile, Γdc is a growing function of αn for n = 2k, where k = 1,2,.... We can, therefore, conclude that IH2 is the main contributor to the 1/f noise upconversion. Consequently, attention to only one auxiliary resonant frequency at 2ω0 appears sufficient [22, 26, 27].

The balance in the rise and fall zero-crossing slopes in Figure 5.10(c) is rooted in the π/2 phase shift between VH1(t) and VH2(t). This is a combination of the π/2 phase difference between IH1(t) and IH2(t) and zero phase of the resistive tank impedance at 2ω0. When ωCM deviates from 2ω0 where |ZCM| and ϕCM are the CM input impedance magnitude and phase, respectively, derived as, where . The ωCM versus 2ω0 misalignment has two effects. The first directly translates ϕCM into the waveform asymmetry. Figure 5.11(a) shows VT2,aux(t) for different ϕCM; α2,aux was chosen as 0.3 to better illustrate the asymmetry. When grossly mistuned from 2ω0, ϕCM could approach ±π/2, thus making the auxiliary resonance completely ineffective. A larger Q-factor of the common-mode resonance, QCM, results in ϕCM closer to ±π/2 for the same 2ω0/ωCM ratios, as illustrated in Figure 5.11(b). The second effect is due to α2,aux, which determines the amount of second harmonic in the voltage waveform. When ϕCM is not zero, Γeff,dc becomes dependent on α2,aux: the larger α2,aux, the more asymmetric waveform and more 1/f noise upconversion. The α2,aux value can be found from the following equation: IH2/IH1 is dependent on the oscillator’s topology. Furthermore, the larger QCM, the larger Rp2 and hence the larger α2,aux. Figure 5.11(c) shows the expected Γeff,dc/Γeff,rms versus ϕCM for different α2,aux. Both of these effects point out that QCM should be low to reduce the sensitivity of this method to the ωCM deviation from 2ω0. Parsitic inductances and capacitances between supply and groud rails can contribute to this deviation. This parasitics become especially important at mmW frequencies [25]. Figure (a) VT2,aux for different ϕCM; (b) ϕCM for different QCM when ωCM deviates from 2ω0; (c) Γeff,dc/Γeff,rms for different α2,aux and ϕCM.

We have shown that if the tank demonstrates an auxiliary CM resonance at the second harmonic of its fundamental ω0 resonance, the oscillation waveform would be symmetric and, hence, the flicker noise upconversion would be suppressed. Since the differential capacitors are not seen by the CM signals (i.e., IH2), a straightforward solution for realizing a CM peak is to design a tank as demonstrated in Figure 5.12(a)) with a set of differential Cd and single-ended (SE) Cc capacitors [26,27]. rp is the equivalent series resistance of the inductor and it is assumed that all capacitors are nearly ideal. This tank shows a fundamental DM resonant frequency, and a CM resonant frequency . From (5.12)–(5.14): Figure (a) A tank with DM and CM resonances; (b) 1/f3 corner of the oscillator employing this tank; (c) ϕCM; and (d) α2,aux of the tank versus ωCM/ωDM. where QDM, Rp2, and Rp1 are, respectively, the quality factor at DM resonance, and impedance peaks at CM and DM resonances. In an extreme condition of Cd = 0, the tank contains only the SE capacitors and reduces to a conventional tank discussed in Section 5.2.2. Targeting ωCM = 2ωDM results in Cd = 3Cc and we can prove that QCM = 2QDM. As discussed supra, the fairly large QCM exacerbates the effects of CM resonance misalignment. To investigate the effectiveness of the proposed method on the tank mistuning sensitivity, we performed an analysis of a 5-GHz voltage-biased class-B oscillator of Figure 5.1(b) with QDM = 10. The oscillator is designed in a 40-nm CMOS technology, and M1,2 are thick-oxide (56/0.27)-μm devices. The power consumption is 10.8 mW at VDD = 1.2 V. As expected, the 1/f3 corner of this oscillator is at its minimum of ∼ 10 kHz at Cd/Cc = 3 (see Figure 5.12(b)). When ωCM deviates from 2ωDM, i.e., Cd/Cc ratio deviates from the ideal value of 3, while keeping Cc + Cd constant, the 1/f3 corner starts to increase from the 10 kHz minimum and reaches its peak at ωCM = 1.7ωDM when the CM resonance phase, ϕCM, gets close to π/2 (about 80° as shown in Figure 5.12(c)). After this point, the ϕCM barely changes, but α2,aux decreases (Figure 5.12(d)) and, consequently, the 1/f3 corner reduces again. The maximum 1/f3 corner of 1.1 MHz is actually much worse than the 400 kHz corner of extreme case when Cd = 0 (see Figure 5.12(b)). This means that if the tank is not designed properly, the performance would be even worse than that without applying this technique. Consequently, to ensure no performance degradation in face of the misalignment, α2,aux at ϕCM ≈ 80° should be less than that of the tank without the applied technique. α2 when Cd = 0 can be found from (5.16): ϕCM = 80°, (5.15) and (5.16) result in Hence, to satisfy this condition, which results in non-practical QDM values. In the following two subsections, we show how to substantially reduce the sensitivity to such misalignment by employing, at no extra area penalty, an inductor exhibiting distinct and beneficial characteristics in DM and CM excitations. The different behavior of a 1:2 turn transformer in DM and CM excitations is also exploited to design a transformer-based F2 tank. With these new tanks, we construct class-D and a class-F oscillators to demonstrate the effectiveness of the proposed method of reducing the flicker noise upconversion. Before we do that, let us compare the 1/f3 corner and current harmonics of a current-biased class-B (see Figure 5.13(a)), a current-biased class-B with noise filtering technique [32] applied to it (see Figure 5.13(b)), and a voltage-biased class-B with the proposed technique applied to it (see Figure 5.13(c)). In the current-biased configuration proposed in [32], a capacitor in parallel with the current source shorts noise frequencies around 2ω0 to ground. An inductor is interposed between the common source of the cross-coupled transistors and the current source. That inductor resonates at 2ω0 with the equivalent capacitor at the common source of the oscillator transistors (see Figure 5.13(b)). The purpose of that resonator is creating a high impedance path at 2ω0 to stop the tank loading when one of the core transistors enters the triode region. That method is also partially effective in reducing low-frequency noise upconversion of core transistors by linearizing the core transistors and reducing current harmonics, especially the second-harmonic component content. That resonator has to be tunable over the tuning range and it increases the die area. Figures 5.13(d–e) show the PN performance and current harmonic components of the three oscillators shown in Figure 5.13(a–c). In the simulations, all the capacitors are ideal capacitors and non-tunable. It is obvious how much the second-harmonic current is reduced in the noise filtering method, and consequently the 1/f3 corner is lower than that in a conventional class-B oscillator. Figure (d) PN and (e) current harmonic components of a class-B oscillator (a), and similar counterparts with noise filtering technique [32] (b) and the proposed method applied (c).

Figures 5.14(a,b) show a 2-turn “F2” inductor when it is excited by DM and CM signals. In the DM excitation, currents in both turns have the same direction, resulting in an additive magnetic flux. However, in the CM excitation, currents have opposite direction and cancel each other’s flux [28]. With the proper spacing between the F2 inductor windings, effective inductance in CM can be made 4x smaller than that in DM. The LDM/LCM inductance ratio is controlled through lithography that precisely sets the physical inductor dimensions and, consequently, makes it insensitive to process variations. Figure 5.14(c) shows the DM and CM inductances and their ratio over frequency. LDM/LCM is close to 4 within a 30%–40% tuning range. Figure A 2-turn “F2” inductor in (a) DM excitation; (b) CM excitation; (c) F2 DM and CM inductances and their ratio; (d) QDM and QCM. Differential capacitors cannot be seen by the CM signals; hence, to be able to set the CM resonance, the F2 tank capacitors should be SE, as shown in Figure 5.15(a). The F2 tank demonstrates two resonant frequencies: ωDM and ωCM. Both of these are tuned simultaneously by adjusting Cc. The precise inductor geometry maintains LDM/LCM ≈ 4 and hence ωCM/ωDM ≈ 2 over the full tuning range. The input impedance of the tank is shown in Figure 5.15(b). Presuming the capacitance losses are negligible, the DM and CM resonance quality factors are The Q-factor of the CM resonance is half that of DM, which relaxes the F2 tank sensitivity to mismatch between ωCM and 2ωDM. For this inductor-based F2 tank, Rp2/Rp1 = 0.25 and the condition in (5.19) is satisfied for Q0 < 15. Furthermore, in the CM excitation, the currents in adjacent windings have opposite direction, which results in an increased AC resistance [29] and so the Q-factor of the CM inductance is even smaller than in (5.21). The Q-factor of LCM inductance of Figure 5.14(b) is about 3–4. Apart from the easy tuning with only one capacitor bank, the mostly SE parasitic capacitors do not play any role in defining the ωCM/2ωDM ratio. Figure (a) Inductor-based F2 tank and (b) its input impedance. Furthermore, the low QCM and, consequently, the lower sensitivity to the ωCM/2ωDM ratio that the inductor-based F2 tank offers make it all more attractive than the tank shown in Figure 5.12(a).

Among the various classes of inductor-based oscillators (e.g., class-B, complementary class-B, class-D [4]), we have decided to validate the proposed method on a class-D oscillator depicted in Figure 5.16(a). This recently introduced oscillator shows promising PN performance in the 1/f2 region due to its special ISF The tail current transistor is removed there and wide and almost ideal switches M1,2 clip the oscillation voltage to GND for half a period (see Figure 5.16(b)) resulting in an almost zero ISF there (Figure 5.16(c)). However, the hard clipping of the drain nodes to GND generates a huge amount of higher-order harmonic currents. Due to the large IH2, in agreement with our analysis, the oscillating waveform has asymmetric fall and rise times (clearly visible in Figure 5.16(b)) and it exhibits a strong 1/f noise upconversion and frequency pushing. A version of class-D with a tail filter technique [32] was also designed in [4] in an attempt to reduce the low frequency noise upconversion. This method is partially effective, lowering the 1/f3 PN corner from 2 to 0.6–1 MHz. Due to the above reasons, this voltage-biased oscillator seems a perfect fit for the proposed method. Figure Class-D oscillator: (a) schematic; its (b) waveforms; and (c) gm-transistor ISF, NMF, and effective ISF. Class-D/F2 oscillator: (d) schematic; its (e) waveforms; and (f) gm-transistor ISF, NMF, and effective ISF; (g) their PN performance; and (h) 1/f3 corner sensitivity to ωCM/ωDM. Figure 5.16(d) shows the proposed class-D/F2 oscillator, which adopts the F2 tank. The gm-devices, M1 and M2, still inject a large IH2 current into the tank, but this current is now flowing into the equivalent resistance of the tank at 2ω0. Clearly, the rise/fall times are more symmetric in the class-D/F2 oscillator, as demonstrated in Figure 5.16(e). The gm-transistors’ ISF, NMF, and effective ISF are shown in Figure 5.16(f). As predicted, effective Γdc is now reduced and the simulated PN performance shows that the 1/f3 corner is lowered from 1 MHz to ∼30 kHz (Figure 5.16(g)). The parasitic inductance LT has to be considered in designing the F2 inductor. Cc controls both CM and DM resonant frequencies simultaneously; hence, any deviation of ωCM from 2ω0 is due to LCM/LDM not being exactly 4 over the TR. To examine the robustness of the tank via simulations, a Cd differential capacitor is deliberately added to the tank. Cc + Cd is kept constant in order to maintain the oscillation frequency. This capacitor shifts down ωDM while keeping ωCM intact. Figure 5.16(h) shows how the 1/f3 corner worsens when Cd/Cc ratio increases. The class-D/F2 oscillator is quite robust to process variations. First of all, due to the low CM resonance quality factor of an F2 inductor, this topology is less sensitive to deviations of ωCM from 2ω0. Furthermore, in this topology, only single-ended capacitor banks are employed; hence, ωCM/ωDM ratio is solely defined by LCM/LDM. The cross-coupled transistor’s parasitic capacitors are mostly single-ended, except for Cgd which is less than 5% of the tank’s total capacitance. Consequently, the modification of core transistors’ parasitic capacitance over process variations will only change oscillation frequency and barely modify the ωCM/ωDM ratio. Figure 5.17(a) shows simulation results for the 1/f3 corner of the class-D/F2 oscillator in different process corners. The PN at 10-kHz offset frequency for both class-D/F2 oscillators for 200 points Monte Carlo simulations on inter/intra die process variations is shown in Figure 5.17(a). Figure Class-D/F2 oscillator: 1/f3 corner over process variation and (b) histogram of PN at 10-kHz offset frequency.

Figures 5.18(a,b) show a 1:2 turns transformer excited by DM and CM input signals at its primary. With a DM excitation, the induced currents at the secondary circulate in the same direction leading to a strong coupling factor, km. On the other hand, in CM excitation, the induced currents cancel each other, resulting in a weak km [30]. The latter means that the secondary winding cannot be seen by the CM signals. “F2” transformer-based tank is shown in Figure 5.19(a). At the DM excitation, no current flows into the metal track inductance, LT, that connects the center tap to the supply’s AC-ground (see Figure 5.19(a)). However, at the CM excitation, the current flowing into LT is twice the current circulating in the inductors. Consequently, the tank inductance Lp in Fig. 5.19(a) is re-labeled as Lpd = Lp in DM and Lpc = Lpd + 2LT in CM excitations. This tank employs SE primary and differential secondary capacitors and demonstrates two DM and one CM resonant frequencies. and if km,DM>0.5, [5]. F2 tank requires ωCM = 2ω0,DM; hence, Figure 1:2 transformer when the primary is excited with (a) DM and (b) CM currents. Figure (a) Transformer-based F2 tank; (b) its input impedance; (c) DM and CM primary and secondary inductance; (d) primary and secondary inductance quality factor and coupling factor; (e) DM and CM resonant frequencies over TR. Unlike in the inductor-based tank, here, the ωCM/ω0,DM ratio is dependent on the secondary-to-primary capacitor ratio. Furthermore, the input impedance Zin, shown in Figure 5.19(b), reveals that QCM is not low, thus making it sensitive to ωCM/ω0,DM. It means the Cs/Cp ratio has to be carefully designed to maintain ωCM/ω0,DM ≈ 2 over the tuning range. In practice, the Q-factor of capacitor banks is finite and decreases at higher frequencies, so QCM will reduce, thus making the tank a bit less sensitive.

As proven in [5], a DM auxiliary resonance at the third harmonic of the fundamental frequency is beneficial in improving the 20-dB/dec PN performance by creating a pseudo-square-wave oscillation waveform (see Figure 5.20(b)). We can merge our transformer-based F2 tank with the class-F3 operation in [5] to design a class-F2,3 oscillator, as shown in Figure 5.20(d–e). To ensure ωCM = 2ω0,DM and ω1,DM = 3ω0,DM, we force LsCs = 3.8LpdCp and km = 0.67. The relatively low km increases the impedance at ω1,DM ≡ 3ω0,DM [31]. However, the class-F3 oscillator meets the oscillation criteria only at ω0,DM. Figure 5.20(e) demonstrates that the pseudo-square waveform of class-F3 oscillation is preserved in the class-F2,3 oscillator. The waveform does not appear to differ much; however, the oscillation voltage spectrum indeed confirms the class-F2,3 operation. IH2 is not very large in this class of oscillators, consequently, the fall/rise-time asymmetry is not as distinct as in the class-D oscillator. However, the 1/f3 corner improvement from 400 kHz in class-F3 to <30kHz in class-F2,3, as demonstrated in Figure 5.20(g), proves the effectiveness of the method. The ISF, NMF, and effective ISFs for these oscillators are shown in Figure 5.20(c,f). Figure Class-F3 oscillator: (a) schematic; (b) its waveforms; and (c) gm-transistor ISF, NMF, and effective ISF. Class-F2,3 oscillator: (d) schematic; (e) its waveforms; and (f) gm-transistor ISF, NMF, and effective ISF; (g) their PN performance; and (h) 1/f3 corner sensitivity to ωCM/ωDM. Class-F2,3 oscillator performance is sensitive to the deviation of ωCM from 2ω0 ≡ 2ωDM. Cp changes both CM and DM resonant frequencies while Cs only changes the DM one. To examine the robustness of the F2 operation, differential capacitors are added in the tank’s primary. Here again Cp,c + Cp,d is constant to maintain the oscillation frequency. Figure 5.20(h) shows the 1/f3 corner versus. ωCM/ωDM ratio and underscores the need to control the capacitance ratio, as per (5.22). Otherwise, a small deviation increases the 1/f3 corner rapidly, and with larger deviations, the method becomes ineffective. The class-F2,3 topology is somewhat less robust to process variations. This topology is generally more sensitive to deviations of ωCM from 2ω0 due to higher CM resonance quality factor. Moreover, in this topology, and is dependent on secondary and primary windings’ inductance and capacitance ratio. The modification of core transistors parasitic capacitance modifies both primary and secondary capacitances and, hence, both DM and CM resonant frequencies are affected in the same direction (they are both going to increase with less parasitic capacitance and vice versa). Therefore, the ωCM/ωDM ratio is not affected drastically with the parasitic capacitance variations; however, due to larger QCM, the small effects are also important. Figure 5.21(a) shows the simulation results for 1/f3 corner of the class-F2,3 oscillator in different process corners. The 1/f3 corner is more affected compared to the class-D/F2 oscillator; however, it is still very competitive. The PN at 10-kHz offset frequency for class-F2,3 oscillator for 200 points Monte Carlo simulations on inter/intra die process variations is shown in Figure 5.21(b). Figure Class-F2,3 oscillator: 1/f3 corner over process variation and (b) histogram of PN at 10-kHz offset frequency. It should be worthwhile to mention that recently a mm-wave class-F23 oscillator considering the second-harmonic current return path was discussed in [35].

The class-D/F2 and class-F2,3 oscillators, whose schematics were shown in Figure 5.16(d) and Figure 5.20(d), respectively, are designed in 40-nm CMOS to demonstrate the suppression of the 1/f noise upconversion. For fair comparison, we attempted to design the oscillators with the same specifications, such as center frequency, tuning range, and supply voltage, as their original reference designs in [4] and [5].

The class-D/F2 oscillator is realized in a 40-nm 1P8M CMOS process without ultra-thick metal layers. The two-turn inductor is constructed by stacking the 1.45 μm Alucap layer on top of the 0.85 μm top (M8 layer) copper metal. The DM inductance is 1.5 nH with simulated Q of 12 at 3GHz. Combination of MOS/MOM capacitors between the supply and ground is placed on-chip to minimize the effective LT inductance, and the remaining uncompensated inductance is modeled very carefully. The capacitor bank is realized with 6-bit switchable MOM capacitors with LSB of 30 fF. The oscillator is tunable between 3.3 and 4.5 GHz (31% TR) via this capacitor bank. M1,2 transistors are (200/0.04)-μm low-Vt devices to ensure start-up and class-D operation over PVT. The chip micrograph is shown in Figure 5.22(a) with core area of 0.1 mm2. Figure 5.23(a) shows the measured PN at fmax and fmin with VDD = 0.5 V. Current consumption is 6 and 4mA, respectively. The 1/f3 corner is 100 kHz at fmax and reduces to 60kHz for fmin. The 1/f3 corner over TR is shown in Figure 5.23(c). The supply frequency pushing is 60 and 40 MHz/V at fmax and fmin, respectively (see Figure 5.23(b)). Table 5.1 compares its performance with the original class-D oscillators (as well as two other relevant oscillators [21, 26] aimed at reducing the 1/f noise upconversion). Compared to the original design, the FoM at 10-MHz offset is degraded in the class-D/F2 oscillator by 3 dB, mainly due to the lack of ultra-thick metal layers, which lowers the inductor’s Q. However, even with this degradation, FoM at 100-kHz offset is improved at least 3 dB. 1/f3 corner is improved at least 10 times versus both class-D and noise-filtering class-D oscillators. Figure Chip micrographs: (a) class-D/F2 oscillator; (b) class-F2,3 oscillator.

The class-F2,3 oscillator is realized in 40-nm 1P7 CMOS process with ultra-thick metal layer. The 1:2 transformer is constructed with the 3.4 μm top ultra-thick (M7 layer) copper metal. The primary and secondary winding inductances are 0.58 and 1.5 nH, respectively, and km = 0.67. The simulated Q-factors of the primary and secondary windings are 15 and 20 at 6 GHz. Like the class-D/F2, the LT inductance has to be compensated with enough decoupling capacitance. The unfiltered part has to be modeled precisely due to the relatively large Rp2. The single-ended primary and differential secondary capacitor banks are realized with two 6-bit switchable MOM capacitors with LSB of 30 fF and 50 fF, respectively. Due to the sensitivity of this oscillator to the frequency mismatch, an 8-bit unit-weighted capacitor bank with LSB of 4 fF is also placed at the primary to tune the DM and CM resonance frequencies. The oscillator is tunable between 5.4 and 7 GHz and the primary and secondary capacitors are changed simultaneously to preserve the class-F2,3 operation. The M1,2 transistors are (64/0.27) μm thick-oxide devices to tolerate large voltage swings. The tail resistor RT bank is realized with a fixed 40-Ω resistor in parallel with 7-bit binary-weighted switchable resistors with LSB size of 5 Ω. This bank can tune the oscillation current from 5–20 mA. The chip micrograph is shown in Figure 5.22(b); the core die area is 0.12 mm2. Figure Class-D/F2 oscillator: measured (a) PN at fmax and fmin; (b) frequency pushing due to supply voltage variation; and (c) 1/f3 corner over tuning range. Table Performance summary and comparison with relevant oscillators Figure 5.24(a) shows the measured PN of the class-F2,3 oscillator at fmax and fmin with VDD = 1 V. Current consumption is 10 and 12 mA, respectively. The 1/f3 corner is 130 kHz at fmax and reduces to ∼60 kHz at fmin. The 1/f3 corner over TR is plotted in Figure 5.24(c). The supply frequency pushing is 23 and 12MHz/V at fmax and fmin, respectively (see Figure 5.24(b)). Table 5.1 compares its performance with the original class-F3 oscillator. Compared to the original design, FoM is degraded about 1–2dB at the 10-MHz offset, which is due to the tail resistor loading the tank more than the tail transistor originally, thus degrading PN slightly. Despite this degradation, FoM at 100 kHz is enhanced by at least 4dB, and the 1/f3 corner is improved 5 times. Figure Class-F2,3 oscillator: measured (a) PN at fmax and fmin; (b) frequency pushing due to supply voltage variation; and (c) 1/f3 corner over tuning range. It might be interesting to point out that class-F2,3 oscillator was adapted for an operation at cryogenic temperatures of 4K [36] where it exhibited a record-low 1/f corner.

In this chapter, we discussed and analyzed a technique to reduce a 1/f noise upconversion in a harmonically rich tank current. We showed that when even-order harmonics of the tank current flow into the capacitive part of the tank, they distort the oscillation waveform by making its rise and fall times asymmetric and hence causing the 1/f noise upconversion. Odd-order harmonics also distort the oscillation waveform; however, the waveform in that case is still symmetric and will not result in the 1/f noise upconversion. We showed how to design a ω0-tank that shows an auxiliary common-mode (CM) resonant peak at 2ω0, which is the main contributor to the 1/f noise upconversion, and showed how oscillation waveform becomes symmetric by the auxiliary resonance. We described how to realize the F2-tank without the die area penalty, by taking advantage of different properties of inductors and transformers in differential-mode (DM) and CM excitations. Class-D/F2 and class-F2,3 oscillators employing, respectively, inductor- and transformer-based F2 tanks are designed in 40-nm CMOS to show the effectiveness of our proposed method. The 1/f3 corner improves 10× in class-D/F2 and 5× in class-F2,3 versus their original counterparts.

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Ultra-low-power (ULP) transceivers underpin short-range communications for wireless Internet-of-Things (IoT) applications. However, their system lifetime is extremely limited by the transceiver power consumption and available battery technology. On the other hand, energy harvesting technologies typically deliver supply voltages that are much lower than the standard supply of CMOS circuits; e.g., on-chip solar cells can supply only 200–800 mV. Although boost converters can bring the level up to the required ∼1 V, their poor efficiency (≤80%) wastes the harvested energy. Consequently, RF oscillators, as one of the transceiver’s most power hungry circuitry, must be very power efficient and preferably operate directly at the energy harvester output. In this chapter, we analyze in depth design of an oscillator topology to address the aforementioned constraints without sacrificing manufacturability and phase purity.

Ultra-low-power (ULP) radios underpin short-range communications for wireless Internet-of-Things (IoT). Since RF transmitters (TX) have consumed a significant portion, if not the majority, of the radio’s power, the IoT system lifetime tends to be severely limited by the TX power consumption and available battery technology. Figure 6.1 shows the system lifetime for various battery choices as a function of current consumption. State-of-the-art Bluetooth Low Energy (BLE) radios [1, 2] consume ∼7 mW and thus can continuously operate no more than 40 hours on an SR44 battery, which has a comparable dimension to the radio module. This directly causes inconvenient battery replacements at least every few months, which limits their attractiveness from the market perspective. The lifetime can be easily increased by employing larger batteries, but that comes at a price of increased weight and dimensions and it is clearly against the miniaturization vision of IoT. This has motivated an intensive research leading to miniaturized transceivers with a high power efficiency [1–12]. Figure BLE system lifetime versus radio current consumption for various battery types. Figure Delivered voltage and power density for various harvester types. Energy harvesting from a surrounding environment can enable and further spur the IoT applications by significantly extending their lifetime. The delivered voltage versus power density of different harvesting methodologies is depicted in Figure 6.2 [10, 13]. Solar cells offer the highest harvested power per area in both indoor and outdoor conditions. However, they provide lower voltages (0.25–0.75 V) than the expected deep-nanoscale CMOS supply of ∼1 V. Hence, boost converters are typically used to bring the supply level up to the required ∼1 V. As can be gathered from Table 6.1, the relatively poor efficiency (≤80%) of boost converters wastes the harvested energy, thus worsening the system-level efficiency, in addition to increasing the hardware complexity coupled with issues of switching ripples. Consequently, it would be highly desirable for the ULP transceivers to operate directly from the harvested voltage. Table Performance summary of state-of-the-art boost converters

	[14] ISSCC’12	[15] ISSCC’14	[16] ISSCC’15
Technology	N/A	65 nm CMOS	0.18 μm CMOS
Input voltage range	0.1–2.9 V	0.15–0.5 V	0.45–3 V
Output voltage range	3 V	0.5–0.6 V	3.3 V
Efficiency @Vin = 0.5 V	≤ 80%	≤ 72.5%	≤ 78.5%

The rest of this chapter is dedicated to introduce and analyze a switching current-source oscillator [17, 18] which is optimized for 28-nm CMOS, can operate directly at the low voltage of harvesters, and reduces power and supply voltage without compromising the robustness of the oscillator start-up or loading its tank quality factor.

The oscillator phase noise (PN) requirements can be calculated by considering the toughest BLE blocking profile: The received packet error rate (PER) must be better than 30.8% while the wanted signal is just 3 dB above the reference sensitivity level of −70 dBm and in face of an in-band blocker of −40 dBm located at 3-MHz offset from the desired channel. Furthermore, the required signal-to-noise ratio (SNR) should be better than 15 dB to support such PER for a GFSK signal with a modulation index m = 0.5 [20]. By replacing the aforementioned values in (6.1), PN shall be better than −105 dBc/Hz at Δω = 2π · 3 MHz. Hence, the PN requirements are quite trivial for IoT applications and can be easily met by LC oscillators as long as Barkhausen start-up criterion is satisfied over process, voltage, and temperature (PVT) variations.Ring oscillators can also satisfy such a relaxed phase noise requirement. However, they consume much higher power than LC oscillators at f0 ≥ 1 GHz [19]. Consequently, reducing oscillator power consumption, PDC, is the ultimate goal in IoT applications. The PN of any class of an RF oscillator (i.e., class-B) at an offset frequency Δω from its resonating frequency ω0 can be expressed as where K is the Boltzmann’s constant; T is the absolute temperature; Qt is the LC-tank quality factor; αI is the current efficiency, defined as ratio of the fundamental current harmonic Iω0 over the oscillator DC current IDC; and αV is the voltage efficiency, defined as a ratio of the single-ended oscillation amplitude, Vosc/2, over the supply voltage VDD [21, 22]. Furthermore, F is the effective noise factor of the oscillator. Equation (6.2) clearly demonstrates a trade-off between the oscillator’s PDC and PN. Furthermore, the oscillator’s FoM normalizes the PN performance to the oscillation frequency and power consumption, yielding The effective noise factor F is expressed by [23, 24] where ϕ = ω0t, is the white current noise power density of the ith noise source and Γi is its relevant ISF function from the corresponding ith device noise [25]. Finally, Rin is an equivalent differential input parallel resistance of the tank’s losses. The oscillator IDC may be estimated by one of the following equations: As a result, the RF oscillator’s PDC is derived by Equation (6.6) indicates that the minimum achievable PDC can be expressed in terms of a set of optimization parameters, such as Rin, and a set of topology-dependent parameters, such as minimum supply voltage (VDD,min), current and voltage efficiencies. Lower PDC is typically achieved by scaling up Rin = Lpω0Qt simply via a large multi-turn inductor, as in [26]. For example, while maintaining a constant Qt, doubling LP would theoretically double Rin, which would reduce PDC by half but at a cost of a 3-dB PN degradation. However, at some point, that trade-off stops due to a dramatic drop in the inductor’s self-resonant frequency and Q-factor. Figure 6.3(a) shows the simulated Q-factor of several multi-turn inductors in 28-nm CMOS versus their inductance values. As the inductor enlarges, the magnetic and capacitive coupling to the low-resistivity substrate increases such that the tank Q-factor drops almost linearly with LP. As can be gathered from Figure 6.3(b), this constraint sets an upper limit on maximum Rin = Lpω0Qt, which is chiefly a function of the technology node. Note that the inductor’s value is largely dependent on its physical dimensions, rather than on the technology. However, the tank Q-factor is a bit degraded in the most recent process nodes (i.e., 28 nm) mainly due to more stringent minimum metal density rules, closer separation between the top-metal and substrate, as well as thinner lower-level metals that are used in metal-oxide-metal (MoM) capacitors. As a consequence, it is expected that Rin(max) slightly reduces by migrating to finer CMOS technologies. Parasitic capacitance of inductor windings, gm-devices, switchable capacitors, and oscillator routings determines a minimum floor of the tank’s capacitance, which appears to be ∼250 fF at f0 = 4.8 GHz. It puts another restriction on Lp and Rin(max) to ∼4.5 nH and ∼1.3 kΩ and sets a lower limit on PDC of each oscillator structure. Under this condition, the tank’s Q-factor drops to ≤9. This explains the poor FoM of RF oscillators in modern BLE transceivers. Figure Dependency of various inductor parameters in 28-nm LP CMOS across inductance value: (a) inductor and tank Q-factor; (b) equivalent differential input resistance of the tank; and (c) required tank capacitance at 4.8-GHz resonance. Note that at this point the inductors are without dummy metal fills. The topology-dependent parameters also play an important role in trying to reduce PDC. Equation (6.6) favors structures that offer higher αI or can sustain oscillation with smaller VDD and αV. On the other hand, αV · αI should be maximized to avoid any penalty on FoM [22, 27], as evident from (6.2). Consequently, to efficiently reduce PDC without disproportionately worsening the FoM, it is desired to employ structures with a higher αI and a lower minimum VDD. To get a better insight, Figure 6.4 shows such effects for the traditional cross-coupled NMOS-only (OSCN) and complementary push–pull (OSCNP) structures [28, 29]. Due to the less stacking of transistors, the VDD,min of OSCN can go 40% lower than that of OSCNP. However, αI of OSCNP is doubled due to the switching of tank current direction every half period. Its oscillation swing, and thus αV, is also 50% smaller. Hence, OSCNP offers ∼3× lower αV/αI. However, both structures demonstrate similar αV · αI product [30]. Consequently, each of them has its own set of advantages and drawbacks such that the minimum achievable PDC and FoM is almost identical, as shown in Table 6.2. Note that applying a tail filtering technique to a class-B oscillator increases its αV [22, 31], which is in line with the FoM optimization but against the PDC reduction, as evident from (6.2) and (6.6). Furthermore, while maintaining the same Rin, a class-F3 operation does not reduce PDC of traditional oscillators since its minimum VDD, αV and αI are identical to OSCN (see Chapter 3). A push-pull class-C oscillator appears as an excellent choice for ULP applications due to its largest αI and smallest αV [32], as per Table 6.2. However, it needs an additional complex biasing circuitry (e.g., an opamp) to guarantee the proper oscillator start-up and to keep the transistors in saturation during the on-state. There are also strong mutual trade-offs between the biasing circuit’s PDC, oscillator’s amplitude stability and PN, much intensified in ULP applications where the tank capacitance tends to be smaller [33]. As a consequence, the biasing circuitry can end up consuming comparable power as the ULP oscillator itself. On the other hand, VDD of class-D oscillators can go below a threshold voltage, Vt. However, due to hard switching of core transistors, its αV and αI are, respectively, higher and lower than other structures [34], as shown in Table 6.2. According to (6.6), this trend is against the PDC reduction. Consequently, the current oscillator structures have issues with reaching simultaneous ultra-low power and voltage operation. Figure VDD,min, αI and αV parameters for: (a) cross-coupled NMOS and (b) complementary push–pull oscillators. Table Minimum PDC for different RF oscillator topologies

Topology	VDDD,min†	αV‡	αI*	PDCmin	αV· αI
OSCN	Vt + VOD ≈ 1.5 Vt	0.66	2/π		0.42
OSCNP	2 Vt + VOD ≈ 2.5 Vt	0.4	4/π		0.51
OSCNP with tail filter	2 Vt + VOD ≈ 2.5 Vt	0.63	4/π		0.8
Class-CNP	2 Vt + VOD ≈ 2.5 Vt	0.25	2		0.5
Class-D	≈ Vt	1.635	0.5		0.82
Class-F3	Vt + VOD ≈ 1.5 Vt	0.66	2/π		0.42
This work	Vt + VOD ≈ 1.5 Vt	0.33	4/π		0.42

† by considering VOD = 0.5 Vt for the current source. ‡ at the minimum VDD. * ideal value. In this chapter, we disclose how to convert the fixed current source of the traditional NMOS topology into a structure with alternating current sources such that the tank current direction can change every half period. Consequently, the benefits of low supply of the OSCN topology and higher αI of OSCNP structure are combined to reduce power consumption further than practically possible in the traditional oscillators.

Figure 6.5 shows an evolution towards the switching current-source oscillator. The OSCN topology is chosen as a starting point due to its low VDD capability. To reduce PDC further, it is desired to switch the direction of the LC-tank current in each half period, which will double αI. Consequently, we beneficially split the fixed current source M1 in Figure 6.5(a) into two switchable current sources, M1 and M2, as suggested in Figure 6.5(b). This allows for the tank to be disconnected from the VDD feed and be moved inbetween the upper and lower NMOS transistor pairs to give rise to an H-bridge configuration. In the next step, the passive voltage gain blocks, A0, are added to the NMOS gates, as shown in Figure 6.5(c). Both upper and lower NMOS pairs should each independently demonstrate synchronized positive feedback to realize the switching of the tank current direction. The “master” positive feedback enforces the differential-mode operation and is realized by the lower-pair transistors configured in a conventional cross-coupled manner. Its negative conductance seen by the tank may be estimated by (see Section 6.4 for detailed calculations) Figure Evolution towards the switching current-source oscillator. On the other upper side, the differential-mode oscillation of the tank is reinforced by the M3,4 devices which realize the second positive feedback.It should be noted that the “master/slave” view is mainly valid from a small-signal standpoint. Both are equally important when considering the large-signal switching operation. The negative conductance seen by the tank into the upper pair can be calculated by (see Section 6.4 for detailed calculations) Equation (6.8) clearly indicates that the voltage gain block is necessary and A0 must be safely larger than 1 to be able to present a negative conductance to the tank, thus enabling the H-bridge switching. By merging the redundant voltage gain blocks, the disclosed switching current-source oscillator is shown in Figure 6.5(d). Note that the tank with an implicit voltage gain can be realized by using a capacitive divider, autotransformer, or step-up transformer, as illustrated in Figure 6.6. The transformer-based tank is chosen in this work due to its simplicity. Figures 6.7 and 6.8 illustrate the novel oscillator schematic as well as waveforms and various operational regions of M1–4 transistors across the oscillation period. The two-port resonator consists of a step-up 1:2 transformer and tuning capacitors, C1, C2, at its primary and secondary windings. The transistors M1,2 set the oscillator’s DC current, while the M3,4 pair acts as a switching current source. Both M1,2 and M3–4 pairs play an equally vital role of switching the tank current direction. As can be gathered from Figure 6.8, Gb oscillation voltage is high within the first half period. Hence, only M2 and M3 transistors are on and the current flows from left to right side of the tank. However, M1 and M4 are turned on for the second half period and the tank’s current direction is reversed. Consequently, just like in the push-pull structure, the tank current flow is reversed every half period, thus doubling the oscillator’s αI to 4/π. Figure Various options of a tank providing voltage gain. Figure Schematic of the switching current-source oscillator. Figure Waveforms and various operational regions of M1–4 transistors across the oscillation period. The VDD of the new oscillator can be as low as VOD1 + VOD3 ≈ Vt, which is extremely small for an oscillator with a capability of switching the tank current direction. This makes it suitable for a direct connection to solar cells. Note that the oscillation swing cannot go further than VOD1,2 at DA/DB nodes, which is chosen ∼150 mV to satisfy the system’s phase noise requirement by a few dB margin. However, the maximum required voltage of the circuit is determined by the bias voltage VB. Equation (6.9) implies that M3,4 should work in weak inversion keeping Vgs3<Vt to achieve lower VDD,min. However, the transistor’s cut-off frequency fmax drops dramatically in the subthreshold operation. Note that fmax should be at least 4× higher than the operating frequency f0 = 4.8 GHz to guarantee the oscillator start-up over PVT variations. This constraint limits Vgs3 ≈ 0.32 V for VOD3 ≈ 150 mV, as can be gathered from Figure 6.9. Consequently, even by considering only the tougher VB requirement, the new structure can operate at VDD as low as 0.5 V, on par with OSCN. Figure fmax of low-Vt 28 nm transistor versus VDS for different VGS. Such a low VDD and oscillation swing can easily lead to start-up problems in the traditional structures. It will certainly increase power consumption, Pbuf, of the following buffer, which would require more gain in order to provide a rail-to-rail swing at its output that is interpreted as a local oscillator (LO) clock. Fortunately, the transformer gain enhances the oscillation swing at M1,2 gates to even beyond VDD, guaranteeing the oscillator start-up and reduction of Pbuf. Consequently, the oscillator buffer is connected to the secondary winding of the transformer in this design. As can be gathered from Figure 6.8, the M3,4 switching current-source transistors operate in a class-C manner as in a Colpitts oscillator, meaning that they deliver more or less narrow-and-tall current pulses. However, their non-zero conduction angle is quite wide, ∼π, due to the low overdrive voltage in the subthreshold operation. On the other hand, M1,2 operate in a class-B manner like cross-coupled oscillators, meaning that they deliver square-shaped current pulses. Hence, the shapes of drain currents are quite different for the lower and upper pairs. However, their fundamental components demonstrate the same amplitude (αI ≈ 2/π) and phase to realize the constructive oscillation voltage across the tank. The higher drain harmonics obviously show different characteristics. However, they are filtered out by the tank’s selectivity characteristic. Note that the current through a transistor of the upper pair will have two paths to ground: through the corresponding transistor of the lower pair and through the single-ended capacitors. Consequently, the single-ended capacitors sink the higher current harmonics of M3,4 transistors.

To calculate a closed-form PN equation, the oscillator model is simplified in Figure 6.10. At the resonant frequency, the transformer-based tank can be modeled by an equivalent LC tank of elements Leq, Ceq, and Rin.The interested reader is directed to [35] for accurate closed-form equations of Leq, Ceq, and Rin. On the other hand, M1–4 transistors with passive voltage gain of the transformer are decomposed into two nonlinear time-variant conductances. Note that the active elements in the circuit may add to the resonator loss, particularly at the extremes of large oscillation waveforms which may push transistors into their triode regions. Consequently, the nonlinearity is decomposed into two nonlinear resistances: one that is always positive, Gds(ϕ), and one that is always negative, Gn(ϕ), where ϕ = ω0t. Further, to get a better insight, the effects of noise on the oscillator phase noise due to channel conductance and transconductance gain of M1–4 transistors are separately modeled in Figure 6.10. All circuit variables in this generic model will be obtained in the following sections.

It is clear that the lower pair is a voltage-biased circuit. Consequently, the noise sources of M1 and M2 are uncorrelated for the entire oscillation period. However, the situation is more complicated for the upper pair. For a short time around zero-crossings, both transistors of the upper pair work in the subthreshold region, while elsewhere one of them is off and the other device will be driven into saturation. In this situation, current through the upper NMOS transistor will have no path to ground other than through the corresponding NMOS transistor of the lower pair if there were no single-ended capacitance at the tank. This phenomenon creates a common-mode oscillation across the tank, which ensures that the drain currents of both lower and upper NMOS transistor are the same. Figure Generic noise circuit model of the disclosed oscillator. However, if the tank includes some single-ended capacitors connected to ground, the oscillator will behave very differently (we also use this single-ended capacitors to create a common-mode resonant frequency at the second harmonic of the fundamental frequency to reduce 1/f noise upconversion). Note that one cannot avoid the presence of single-ended capacitors in the tank due to drain–bulk and drain–source parasitic capacitance of lower-pair transistors, source–bulk and drain–source parasitic capacitance of upper pair transistors, and parasitic capacitance of the transformer’s primary winding. In this situation, the current through transistors of upper pair will have two paths to the ground: through the corresponding NMOS transistor of the lower pair and through the single-ended capacitors. Consequently, single-ended capacitors suppress the common-mode oscillation voltage across the tank. In this instance, the upper pair is more appropriately viewed as a voltage-biased circuit. Consequently, noise sources due to transconductance gain of M1–4 transistors are absolutely uncorrelated. By using the same approach as [36], we are going to replace all noise sources with an equivalent noise source across the tank. By writing KCL at DA and DB nodes, it is straightforward to show that the instantaneous equivalent current can be calculated by (see Figure 6.11) As a consequence, the resulting differential noise current through the tank is Figure Simplified schematic of the switching current-source oscillator. Figure Simplified schematic of the lower pair of the oscillator.

The negative conductance of lower and upper pairs will be calculated separately in the following sections. The upper and lower negative conductances are in parallel. Hence, the total negative conductance is calculated by adding the negative conductance of lower and upper pairs. The gate-source voltage of M1 is calculated by (see Figure 6.12) As a result, the derivative of gate–source voltage of M1 is calculated by The transconductance gain of M1 transistor may be estimated by We can rewrite Equation (6.14) as On the other hand, the gate-source voltage of M2 is calculated by And again, we can rewrite Equation (6.16) as The effective negative conductance of lower pair, By using (6.15) and (6.17), the above equation can be rewritten by The same calculations can be done for M3 and M4. The gate–source voltage of M3 is calculated by (see Figure 6.13) As a result, the derivative of gate–source voltage of M3 is calculated by Figure Simplified schematic of the upper pair of the oscillator. The transconductance gain of M3 transistor may be estimated by We can rewrite the above equation by On the other hand, the gate–source voltage of M4 is calculated by As a result, the derivative of gate–source voltage of M4 is calculated by The transconductance gain of M4 transistor then is estimated by We can rewrite the above equation by The negative conductance of upper pair By using (6.23) and (6.27), the above equation can be rewritten by The upper and lower negative conductance are in parallel. Hence, the total negative conductance is calculated by

The positive conductance of lower and upper pairs will be calculated separately in the following sections. The upper and lower positive conductance are in parallel. Hence, the total positive conductance is calculated by adding the positive conductance of lower and upper pairs. The drain–source voltage of M1 is calculated by (see Figure 6.12) As a result, the derivative of drain–source voltage of M1 is calculated by The drain–source conductance of M1 transistor may be estimated by We can rewrite the above equation by On the other hand, the drain–source voltage of M2 is calculated by As a result, the derivative of drain–source voltage of M2 is calculated by The drain–source conductance gain of M2 transistor may be estimated by We can rewrite the above equation as The positive conductance of lower pair then will be Using (6.34) and (6.38), we can conclude: The drain–source voltage of M3 is calculated by (see Figure 6.13) As a result, The drain–source conductance gain of M3 transistor then is estimated by We can rewrite the above equation as On the other hand, the drain–source voltage of M4 is calculated by As a result, and We can rewrite the above equation as The positive conductance of upper pair then will be Using (6.44) and (6.48), we can conclude The upper and lower positive conductance are in parallel. Hence, the total negative conductance is calculated by

To sustain oscillation, the average power dissipated in the tank (Rin) and positive conductance of active devices (Gds(ϕ)) must equal the average power delivered by the negative conductance of nonlinearity (Gn(ϕ)) [36]. Hence, Assuming Vout = Accos(ω0t), the average power dissipated in the tank can be calculated by The current drawn by the positive conductance of nonlinearity can be described as and the average power dissipated by the positive conductance of the nonlinearity is If we switch the order of the integrals, we may write We know and where Gds[k] describes the Fourier series coefficients of the instantaneous positive conductance of nonlinearity Gds(t). By replacing (6.57) and (6.58) in (6.56) We also define, By replacing (6.60) in (6.59), Now let us calculate the average power delivered Gn(ϕ). The current drawn by the Gn(ϕ) can be described as and the average power dissipated by the positive conductance of the nonlinearity is If we switch the order of the integrals, we may write Consequently, To sustain oscillation, the average power dissipated in the tank (Rin) and positive conductance of active devices (Gds) must equal the average power delivered by the negative conductance of nonlinearity (Gn). By replacing (6.53), (6.61) and (6.65) in (6.52), Consequently, On the other hand, the total effective negative conductance can be rewritten as sum of the effective negative conductance of lower and upper pairs Note that both upper and lower NMOS pairs should each individually demonstrate synchronized positive feedback to realize the switching of the tank current direction. Consequently, as with traditional complimentary oscillator, each pair should roughly compensate half of the oscillator losses. On the other hand, GNDEF and GNUEF can be, respectively, calculated by and By merging (6.70), (6.71) and (6.69), we have Since the oscillator is a symmetric circuit, the effective transconductance of M1 and M2 (also, M3 and M4) are the same. Hence, we can rewrite the above equation by and We will use (6.74) and (6.75) later for calculating a closed-form equation of this oscillator.

It is well known that the phase noise and FoM of any RF oscillator at an offset frequency ω0 from its resonating frequency ω0 = 2πf0 can be expressed by and, where K is the Boltzmann’s constant; T is the absolute temperature; Qt is the LC-tank quality factor; αI is the current efficiency, defined as ratio of the fundamental current harmonic Iω0 over the oscillator DC current IDC; and αV is the voltage efficiency, defined as ratio of single-ended oscillation amplitude Vosc/2 over the supply voltage VDD. F is the oscillator’s effective noise factor and estimated by Let us now calculate the contribution of the losses and active devices. The white current noise power density of the resistive loss of the oscillator is given by The relevant impulse sensitivity function of noise sources associated with a sinusoidal waveform oscillator, Vosc · cos(ϕ), may be estimated by Γ = sin(ϕ) [25, 28]. By exploiting (6.4), the effective noise factor due to resistive losses of the oscillator becomes where GDS[k] describes the kth Fourier coefficient of the instantaneous Gds(ϕ). From (6.51) and since the oscillator is a symmetric circuit, . Consequently, we can rewrite (6.80) as To get a better insight, different components of the above equation are graphically illustrated in Figure 6.14(a)–(c). The literature interprets RinGDSEF term in (6.81) as the tank loading effect. In our design, M1 and M2 alternatively enter the triode region for part of the oscillation period and exhibit a large channel conductance. As shown in Figure 6.14(a), simulated 0.5RinGDS1EF can be as large as 0.6 for the lower-pair transistors. However, M3,4 work only in saturation and demonstrate small channel conductance for their entire on-state operation, as evident from Figure 6.14(a). Hence, the simulated value of 0.5RinGDS4EF is as low as 0.15 for upper pair transistors. Note that both NMOS and PMOS pairs of the OSCNP structure simultaneously enter the triode region for part of the oscillation period and load the tank from both sides. In this structure, however, only one side of the tank is connected to the AC ground when either M1/M2 is in triode while the other side sees high impedance. Hence, this structure at least preserves the charge of differential capacitors over the entire oscillation period. Consequently, compared to the traditional oscillators, the tank loading effect is somewhat reduced here. Figure Circuit-to-phase-noise conversion across the oscillation period in the switching current-source oscillator. Simulated (a) channel conductance of M1–4; (b) conductance due to resistive losses; (c) noise factor due to losses; (d) transconductance of M1–4; (e) effective noise factor due to transconductance gain; (f) effective noise factors due to different oscillator’s components. The effective noise factor due to transconductance gain can be calculated by Replacing (6.11) in (6.82), By replacing (6.72) and (6.73) in (6.83), To get a better insight, different components of the above equation are graphically illustrated in Figure 6.14(d–e). As discussed in conjunction with Figure 6.5(c), the transformer’s passive voltage gain, A0, covers a significant part of the required loop gain of the lower positive feedback. Hence, the lower-pair transistors have to compensate only 1/(2A0) of the circuit losses. For the upper positive feedback, however, A0 covers a smaller part of the required loop gain. Consequently, the upper transistors should work harder and compensate 1/(2(A0−1)) of the oscillator loss. Consequently, as (6.84) indicates, the GM noise contribution by the lower pair is smaller. However, its effect on Floss is larger such that both pairs demonstrate more or less the same contribution to the oscillator PN (see Figure 6.14(f)). Finally, the total oscillator effective noise factor is given by To obtain the oscillator phase noise, GDS1EF and GDS4EF should also be calculated or simulated. Since transistor size and oscillation waveforms are known, it is pretty straight-forward to calculate a closed-form equation for them. However, the final equation will be huge and these parameters are calculated numerically here. When M3,4 are not turned off, they work only in saturation and thus their channel conductance and GDS4EF are negligible. However, as shown in the manuscript, precise simulations show that can be as large as 0.15 even if the transistor works only in the saturation. It translates to 0.6 dB higher noise factor for this oscillator due to channel conductance noise of M3,4 transistors. On the other hand, M1 and M2 alternatively enter the triode region for part of the oscillation period. Hence, their effective conductance GDS1EF is larger. Simulations show that is about 0.6 in this oscillator. We will also show later that the excess noise factor of NMOS transistors is 1.4. The voltage gain is 2.16. By replacing those numbers in the nose factor equation, we have the noise factor is just 1.5 dB higher than the ideal value of (1 + γ), despite the aforementioned practical issues of designing ulta-low voltage and power oscillators. The phase noise and FoM of this oscillator can be calculated by replacing (6.85) in (6.2).

Several techniques have been exploited to improve the oscillator’s 1/f noise upconversion. First, dynamically switching the bias-setting devices M1,2 will reduce their flicker noise, as also demonstrated in [37]. It also lowers a DC component of their effective impulse sensitivity function. Second, as discussed in Chapter 5, [38, 39], a second-order harmonic of the gm-devices’ drain current flows into the capacitive part of the tank due to its lower impedance and creates asymmetric rise and fall times for the oscillation waveform. It directly increases a DC value of the oscillator ISF and thus its 1/f3 PN corner. This phenomenon can be alleviated by realizing an auxiliary resonance at 2ω0 such that the second harmonic current flows into equivalent resistance of the tank in order to avoid disturbing the rise and fall time symmetry of the oscillation voltage. Since common-mode signals, such as a second harmonic of the drain current, cannot see the tuning capacitance at the transformer secondary winding [21], the auxiliary 2ω0 can be realized without die area penalty and by adjusting the single-ended capacitance at the transformer primary winding [39]. The last source of the 1/f noise is MB1 in the biasing circuitry. By exploiting long channel device for biasing, its power consumption becomes negligible compared to the oscillator core while MB1/B2 occupy larger area and thus generate lower 1/f noise. Consequently, based on aforementioned techniques, a lower 1/f3 PN corner is expected than in the traditional oscillators.

The transformer-based tank’s input equivalent resistance, Rin, and voltage gain, A0, should be maximized for the best system efficiency. Both optimization parameters are a strong function of ζ = L2C2/L1C1 [35], as shown in Figure 6.15. Rin may be estimated by Figure Transformer-based tank: (a) schematic; (b) input parallel resistance; (c) voltage gain; and (d) R21 versus ζ-factor. where , and Q1 and Q2 are, respectively, the Q-factors of the transformer’s primary and secondary windings. It can be shown that Rin reaches its maximum when Note that the tank Q-factor is maximized at different ζ = Q2/Q1 [24]. The maximum Rin is obtained by inserting (6.88) into (6.87) Consequently, the transformer’s coupling factor km enhances Rin by a factor of at ζRmax. For this reason, the switched-capacitor banks are distributed between the transformer’s primary and secondary to roughly satisfy (6.88). For km ≥ 0.5, the voltage gain of the transformer-based tank may be estimated by As shown in Figure 6.15(c), A0 increases with larger ζ. Note that larger Rin and A0 are desired to reduce PDC and Pbuf, respectively. To consider both scenarios, trans-impedance R21 = Rin · A0 term is defined and depicted in Figure 6.15(d). R21 reaches its maximum at ζ = 1 for Q1 ≈ Q2, which is reasonable for monolithic transformers. We also define the maximum of R21 as the transformer . Consequently, the transformer dimensions and winding spacing are chosen to maximize this term.

The oscillator was prototyped in TSMC 40 nm 1P7M CMOS. The chip micrograph is shown in Figure 6.16(a). M1,2 and M3,4 transistors are minimum-length low-Vt devices with a width of 32 and 256 μm, respectively. The transformer’s primary and secondary differential self-inductance is only 660 pH and 2 nH, respectively, with the coupling factor km = 0.76. Both transformer’s winding are realized with top ultra-thick metal (3.5 μm). However, the transformer includes a floating M1-to-M6 shield to comply with the strict metal density rules (>10%–20%) for manufacturability and also to alleviate the substrate loss. Note that the shield must be significantly thinner than the skin depth at the desired frequency to avoid any attenuation of the magnetic field. The skin depth of copper is ∼0.9 μm at 5 GHz. However, the thickness of M6 layer is 0.85 μm. Hence, adding M6 dummy metal reduces the transformer’s magnetic field, inductance, and Q-factor, and thus Rin drops by 10%–20%. The simulated Q-factor is 12 and 16 for the primary and secondary windings, respectively. Figure (a) Chip micrograph; (b) measured oscillator phase noise and FoM at 3-MHz offset frequency across the tuning range. Figure 6.17 shows the measured PN at the highest and lowest frequencies (fmax, fmin) with VDD of 0.5 V and PDC of 470 and 580 μW, respectively. Thanks to the switching current-source technique, 1/f3 PN corner of the oscillator is relatively low and varies between 250 and 420 kHz across the tuning range (TR). The oscillator has a 22.2% TR, from 4 to 5 GHz. Figure 6.16(b) displays plots of phase noise and FoM across the TR. The FoM reaches maximum 189.9 dBc at fmax and varies ∼1 dB across the TR. Figure Measured phase noise of this oscillator. Table Comparison table of low power oscillators

	This Work	[40] JSSC’05	[23] JSSC’08	[41] ESS-CIRC’14†	[26] ISSCC’14
Technology	40 nm	0.18 μm	0.13 μm	28 nm	40 nm
VDD	0.5 V	0.5 V	1 V	0.5 V	1 V
TR(%)	22.2	8.7	14	N/A	24.5
f0(GHz)	4.8	3.8	4.9	2.35	2.44
PN (dBc/Hz)‡	−139	−143	−149.5	−125.8	−131.1
PDC (mW)	0.48	0.57	1.4	0.38	0.4
FoM (dB)	189.8	193	195.5	187.5	183
FoMT (dB)*	196.7	191.7	198.5	N/A	190.8
Freq pushing	17 MHz/V	273 MHz/V	N/A	N/A	N/A
Dummy fill	Yes	No	No	No	No
Area (mm2)	0.14	0.23	0.11	0.2	0.15
Oscillator topology	Switching current source	TRX feedback	Class-C	Class-D	Traditional

†Including LDO. LDO also performs a start-up role. ‡At Δf = 10 MHz normalized to 2.4-GHz carrier. *FOMTT = |PN|+20 log₁₀((f0/Δf)(TR/10)) − 10log10(PDC(mW)). Table 6.3 summarizes the oscillator performance and compares it with relevant state-of-the-art for PDC<2 mW and TR>8%. It is the only one with the all-layer dummy metal fills inside the LC tank for manufacturability. For the similar PDC (400–600 μW), only the transformer-feedback VCO [40] shows better FoM but with a much larger area, lower TR, and extremely high frequency pushing. Class-C VCO [23] also shows better FoM but at a much higher PDC. Furthermore, it needs additional complex biasing circuits (such as opamp) for proper operation, which can potentially limit its minimum VDD and thus PDC. It might be interesting to point out that switching current source oscillator is already adapted in a fractional-N ADPLL for BLE [42], in a fully integrated BLE transmitter [18], and a BLE transiver [43].

A switching current-source oscillator has been described and analyzed, providing deep insights into beneficial circuit operation. It combines advantages of low supply voltage operation of the conventional NMOS cross-coupled oscillator with high current efficiency of the complementary push–pull oscillator to reduce the oscillator supply voltage and dissipated power without sacrificing its start-up robustness or loading tank’s Q-factor. The 28-nm CMOS prototype exhibits 189.5 dBc/Hz FoM, with 22% tuning range, dissipating 0.5 mW from 0.5 V power supply, while complying with the process technology manufacturing rules.

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In this chapter, we introduce a method to broaden a tuning range of a CMOS LC-tank oscillator without sacrificing its area. The extra tuning range is achieved by forcing a strongly coupled transformer-based tank into a common-mode resonance at a much higher frequency than in its main differential-mode oscillation. The oscillator employs separate active circuits to excite each mode but it shares the same tank, which largely dominates the core area but is on par with similar single-core designs. The tank is forced in common-mode oscillation by two injection locked Colpitts oscillators at the transformer’s primary winding, while a two-port structure provides differential-mode oscillation. An analysis is also presented to compare the phase noise performance of the dual core oscillator in common-mode and differential-mode excitations. A prototype implemented in digital 40 nm CMOS verifies the dual mode oscillation and occupies only 0.12 mm2 and measures 56% tuning range.

Oscillator design for multi-mode multi-band (e.g., Fourth or Fifth Generation (4G/5G) cellular) applications demands wide tuning range (TR) while ensuring sufficiently low phase noise (PN) for a range of targeted frequency bands. The maximum achievable TR of a traditional single-core LC-tank oscillator is limited at 35%–40% by a Con/Coff capacitance tuning ratio of its switched-capacitor network, further constrained by large size of its switches needed to prevent deterioration of the LC tank’s quality (Q)-factor. For example, the Q-factor of a switched-capacitor network in a 40 nm technology is about 80 at 4 GHz resonant frequency when Con/Coff = 2. For an inductor’s Q-factor of 15 at this frequency, the tank’s equivalent Q-factor reduces to 12.6. The most straightforward solution seems to be designing two separate oscillators [1,2] at the expense of large area, and the need for high-frequency source-selecting multiplexers, which increase power consumption and noise floor. A system-level local oscillator (LO) solution in [3] uses a single 40-GHz oscillator followed by a ÷2 divider and an LC-tank mixer to generate 20 and 30 GHz LO signals. However, the extra mixer costs significant power and area as well as it produces spurs. Another attempt is to decrease the area of a two-core oscillator by placing one inductor underneath the other [4, 5]. However, the top inductor has to be very large so that the other one can be placed at its center without degrading the top inductor’s quality factor. Therefore, the oscillator area is still considerably larger than that of a single-tank oscillator. Employing switched resonator tanks, in which the tank’s inductance is controlled by turning on/off interconnecting switches, is another TR expanding technique [6–13]. However, the switches’ resistance limits the tank’s Q-factor, thus degrading the oscillator PN [14]. Transformer-based dual-band oscillators [15, 16] offer wide but not continuous tuning range. A switched-shielded transformer [17] is another method to increase the oscillator’s tuning range but it appears effective only at mm-wave frequencies. A shielded inductor [18] with a shorting switch is inserted between two windings of a transformer [17]. The coupling factor between the windings changes as to whether the current is flowing in the shielded inductor or not. This transformer is not large; however, its inductors’ quality factor gets compromised. Consequently, this range-increasing technique is interesting for mm-wave applications where the tank’s quality factor is rather limited by the capacitive part; however, for the single-GHz RF frequencies, the degradation of the tank’s Q-factor would seem to be excessive. Recent works on mode-switching oscillators significantly improve the PN versus TR trade-off [19–21]; however, they do not improve the TR versus die area trade-off. For example, Li et al. [20] switches between resonant modes (even/odd) of two capacitively and magnetically coupled LC resonators, as shown in Figure 7.1(a). Strong magnetic coupling enhances the difference between the two resonant frequencies; hence, a continuous TR extension calls for a low coupling factor, such that the transformer ends up to be quite large. Unfortunately, the recent CMOS technology nodes (28 nm and, to a lesser extent, 40 nm) have brought about very tough minimum metal-density requirements; therefore, the inductors and transformers should be filled with a lot of dummy metal pieces [22]. This has negative consequences on inductors as resistive losses due to eddy currents in the dummy fills degrade the Q-factor. And, that is in addition to increasing the parasitic capacitance, thus narrowing the TR. The losses are even more severe in the weakly coupled transformers. The spacing between their primary and secondary windings is larger (see Figure 7.1(a)) and must be filled with dummy metal pieces, but it is precisely where the magnetic flux is concentrated the most. Figure LC tanks for wide tuning range: (a) resonant mode switching technique [20]; (b) band switching technique [21]; (c) introduced technique in [33, 34]. In [21], as shown in Figure 7.1(b), four identical inductors are coupled through four mode-switching transistors, providing two oscillation bands. In a low-band oscillation mode, there is no AC current flow possibility in two of these inductors (see Figure 7.1(b)); however, in a high-band mode, the AC current can flow in all the inductors. Thus, the effective inductance value in each band could be controlled. Obviously, the four inductors significantly increase the area. Considering that not all applications require as stringent PN performance as does cellular wireless, we concentrate in this chapter on maintaining the die area similar to that of a single LC-tank oscillator, while significantly improving the TR and keeping a reasonable PN performance. The single-tank oscillator employs a strongly coupled transformer-based tank and forces the tank to oscillate either in a differential mode (DM) or common mode (CM); see Figure 7.1(c) [33, 34]. The DM oscillation provides the TR equivalent of a single-tank oscillator. The TR is then extended by the CM oscillation. The oscillator has two separate active circuits to excite each mode. However, since the passive part is shared in both modes, the die area is comparable to that of a typical narrow TR oscillator. In Section 7.2, we briefly analyze the mode-switching oscillator introduced in [20]. Section 7.3 describes how the transformer-based tank can exhibit both DM and CM resonances. Section 7.4 describes a circuit implementation of the single-tank two-core oscillator that excites one of these resonances at a time. Section 7.5 shows measurement results.

As we mentioned before, in this technique, two capacitively and magnetically coupled LC resonators are replaced a simple resonator to widen oscillator bandwidth. The input impedance of the transformer-based tank, shown in Figure 7.2(a), has a fourth-order polynomial denominator and shows two resonant frequencies, where , and . The oscillator built around a transformer tank can excite ωL or ωH at a time to expand its tuning range. However, the different impedances of these resonances (see Figure 7.2(b)) results in a large gap in PN performance of the oscillator in two modes. A tank can also be capacitively coupled as shown in Figure 7.2(c). Two sides of the transformer can be forced to oscillate either in phase or 180° out of phase with the help of four switches (see Figure 7.3(a)) [20]. When oscillation is in phase, high-frequency band (HB), the coupling capacitor cannot be seen. Assuming L1 = L2 = L and C1 = C2 = C, Figure (a) Transformer-based tank and (b) its input impedance; (c) capacitively coupled transformer-based tank and (d) its input impedance. Figure (a) Simplified schematic of DCO; (b) DCO operates in HB; and (c) LB. However, if the two sides of the transformer are forced to oscillate out of phase, there will be a virtual ac ground in the middle of CC, as shown in Figure 7.3(c). Therefore, the oscillator is switched to the low-frequency band (LB). The output frequency is obtained as follows: where CC is the coupling capacitance between the two windings. A low coupling factor of the transformer, km, ensures that the separation between high-band and low-band frequencies is in a way that a continuous oscillation is possible. The equivalent parallel resistance of the two modes of the resonators can be found as follows [20]: in which rs is the equivalent series resistance of the primary and secondary inductances. These four design parameters, km, CC, C, and L, are used to design an oscillator with continuous tuning range and some frequency overlap between the oscillation modes, while making possible Rp,HB ≈ Rp,LB (Figure 7.2(d)) to ensure balanced performance in the two modes. The coupled tank resonates at one of these modes (bands) depending on the G1 and G2 transconductances states (see Figure 7.3(a)). When G1’s are on and G2’s are off, two sides of the tank oscillate at the same phase. In the opposite state, G1’s are off and G2’s are on, so the two sides of the resonator oscillate out of phase. In order to avoid the frequency discrepancy between HB and LB, CC and km are chosen to provide some frequency overlap between the two oscillation bands and also assure almost equable phase noise performance in both modes [20]. The transconductances are designed as differential cells as is shown in Figure 7.4. We designed a wide tuning range oscillator with this technique. It employs a transformer with L = 700 pH and km = 0.18 [32]. The transformer characteristics are shown in Figure 7.5(a–c). L1 and L2 are well designed to have more or less the same inductance. Although L2 is considerably larger than L1, however its quality, Q2, factor is still 1.7 times less than Q1. Figure Differential transconductance schematic. Figure (a) Inductance and (b) quality factor of the transformer’s primary and secondary winding. (c) The coupling factor. (d) Chip micrograph. The oscillator is designed and realized in SMIC 40 nm 1P7M CMOS process. VDD is chosen to be 0.6 V and the oscillation frequency is 3.6–5.02 GHZ (32% tuning range) in LB and 4.6–6.94 GHz (40% tuning range) in HB, resulting in a total of 65% tuning range. The PN performance of the fmax, fmid, and fmin in LB and HB modes are shown in Figure 7.6 and Figure 7.7, respectively. The M1–M4 transistor sources are connected to ground; consequently, the amount of tank’s current harmonic is relatively large. In agreement with our discussion in Chapter 5, the 1/f3 corner is relatively large in this oscillator. For the same reason, the frequency pushing of this oscillator is also relatively high as is measured and shown in Figure 7.8. The chip micrograph is shown in Figure 7.5(d). Active die area is about 0.24 mm2 which is about two times larger than the rest of single tank oscillators we studied so far in this book. In Section 7.3, we study in detail a dual mode wide tuning range oscillator with an area of a single tank oscillator. Figure PN of the oscillator in the LB. Figure PN of the oscillator in the HB. Figure Oscillation frequency dependency on supply voltage for different frequency bands.

A transformer-based tank, depicted in Figure 7.9(a), exhibits two DM resonant frequencies. If this transformer possesses a strong magnetic coupling factor, km, its leakage inductance would be small and so the second DM resonant frequency would be much higher than the main one. Consequently, we would not get a continuous extension of the TR by forcing the oscillation at the second DM resonant frequency. On the other hand, in order for the transformer size to be not much larger than that of an inductor, km > 0.6 appears a necessary condition. With this constraint, the first resonance can be estimated as [24] Figure (a) A transformer-based tank; (b) limited DM and CM TR due to Cs, c; 1:2 turn transformer: (c) DM excitation; (d) CM excitation; and (e) tank’s input impedance. where Lp and Cp are primary, and Ls and Cs are secondary windings’ inductances and capacitances. The approximation error of (7.6) from the exact resonant frequency (Equation (5) in [24]) is less than +6% for km ≥ 0.7. Abandoning the hope of exploiting the second DM resonance, suppose now this tank is excited by CM signals, and, for now, we assume that primary and secondary winding inductances and km are similar in DM and CM excitations. CM signals cannot see the differential capacitors; thus, the tank can only exhibit CM resonances when these capacitors are single-ended. If this tank were to employ only single-ended primary and differential secondary capacitors, the secondary winding inductances and capacitances would not affect the CM characteristics of the tank, e.g., resonant frequency. This tank will show a single CM resonance at The difference between the CM and DM resonance frequencies, i.e., Equations (7.7) and (7.6), suggests a new possibility for extending the tuning range toward higher frequencies, provided we can build an oscillator around this transformer-based tank that can excite it with either DM or CM signals, without adding any bulky passive components. To investigate how much tuning range we can expect from a single tank, we assume that the tank employs a switched capacitor bank with a 2:1 capacitance switching ratio: This ratio should guarantee a sufficiently high Q-factor of switched-capacitors in recent CMOS technologies. With this assumption, in both modes and, thus, both DM and CM resonant frequencies (Equations (7.6) and (7.7)) will tune by . To avoid any gaps between the DM and CM tuning ranges, at least ωCM,low = ωDM,high. Hence, With these conditions, the resonant frequency could theoretically cover an octave while going from DM to CM oscillations. Practically, Cmax/Cmin has to be >2 due to parasitics and difficulty with controlling the precise overlap between the DM and CM resonances. One limiting factor in the tuning range of such an oscillator is the single-ended parasitic capacitance throughout the secondary winding side. If the CM coupling factor, km,c, were hypothetically similar to the DM one, km,d, and km,c = km,d > 0.6, then the CM resonance would shift down to , where Cs,c is the total of single-ended capacitances on the secondary side (Figure 7.9(a)). At the same time, the DM resonance would also shift down to . Interestingly, satisfying the overlap between CM and DM oscillations with the condition in (7.8) results in the same constraint as (7.9). However, the fixed parasitic capacitance, Cs,c, degrades the CM oscillation tuning range more than it degrades the DM oscillation tuning range; see Figure 7.9(b). A 1:2 turns-ratio transformer, which has distinctly different characteristics in DM and CM excitations, relieves such a degradation. Figures 7.9(c,d) show this transformer when its primary is excited, respectively, with DM or CM signals. In the DM excitation, the induced currents at the two sides of the secondary winding circulate constructively in the same direction, thus creating a strong coupling factor between the transformer windings, while in the CM excitation these induced currents cancel each other within each full turn of the secondary winding (i.e., from the secondary’s terminal to the secondary’s center-tap), leading to a weak coupling factor [23]. This weak km,c can be interpreted as the secondary winding not being seen from the primary and, therefore, the secondary’s single-ended capacitors have an insignificant effect on the tank’s CM resonant frequency. Assuming the capacitor bank is almost ideal, at least compared to the lossy inductors represented by the rp and rs equivalent series resistances of the primary/secondary windings, CM resonance has the quality factor of QCM = Qp = Lpω/rp, which is similar to that of an inductor-based tank. The high Q-factor of this resonance indicates that with an appropriate active circuitry, the CM oscillation of a reasonable quality would be possible. The DM and CM input impedances of this tank are shown in Figure 7.9(e). The single-ended switched capacitors require two switches to provide a ground connection in the middle, which results in a 50% lower Q-factor as compared to a differential switched capacitor with the same switch size. This would appear as a disadvantage of our new technique; however, that is not the case. Let us compare the tuning range of a typical inductor-based tank oscillator employing the differential capacitor bank with our transformer-based tank oscillator employing the single-ended primary and the differential secondary capacitor banks. The equivalent capacitance of this bank varies from Con,D = Cp to , where Cpar is the parasitic capacitance of the switch (see Figure 7.10(a)). For a typical Coff,D/Con,D value of 0.5 (Cpar = Cp), the inductor-based oscillator employing this tank would exhibit . Figure (a) Differential and (b) single-ended capacitor banks. The width of each switch in the single-ended switched-capacitor bank should be twice the width of each differential counterpart for the same Q-factor. Consequently, (see Figure 7.10(b)). Employing this capacitor bank in a transformer-based tank at the primary winding and employing the differential bank at the secondary winding, and benefiting from the impedance transformation of the 1:2 turns-ratio transformer (Ls/Lp ≈ 3), results in , which is very close to the inductor-based tank tuning range.

Forcing the transformer-based tank to resonate in DM is quite straightforward. The oscillator can be realized as a one-port or a two-port structure [25, 26]. However, only the two-port structure will guarantee a reliable start-up at the first DM resonance [24], thus preventing the mixed DM oscillation. A separate active circuit is now needed to force the tank into the CM resonance. Colpitts and Hartely topologies are two well-known examples of single-ended oscillators. Invoking our ground principle of sharing the same tank by the active CM and DM circuits, the Coplitts structure is consequently chosen. To improve the PN, two mutually injection-locked Colpitts oscillators share the primary inductor. The schematic of the novel dual core oscillator is shown in Figure 7.11(a). To avoid the dual oscillation, only one active circuit core is turned on at a time. Figure Dual core oscillator: (a) schematic; (b) overlap and octave oscillation conditions; and (c) tuning range. The left side of Figure 7.11(a) is the two-port DM oscillator. In this mode, VB2 = VB3 = 0V, M7 switch is on biasing M1,2, while M8 switch is off. The waveforms are shown in Figure 7.12(a,b). The transformer has the 1:2 turns ratio and its gain reduces the M1,2 noise upconversion to PN, and also results in a larger gate voltage compared to drain voltages, which facilitates oscillation start up. The right-hand side of the oscillator schematic are two locked single-ended Colpitts oscillators. M8 switch is now turned on to ensure the in-phase operation of the two Colpitts oscillators, without which the two cores might exhibit an arbitrary phase shift. In this mode, VB1 = 0V to turn off the differential oscillation. M7 switch is also off to minimize the CM inductive loading on the primary winding by the secondary one. Both single-ended oscillators start at the same frequency but could be slightly out of phase; subsequently, they lock to each other and there is no phase shift between them. The locking of the two oscillators gives an additional 3-dB PN improvement. Waveforms are shown in Figure 7.12(c,d). Note that an attempt of simplifying the CM structure by removing M8 and permanently shorting the sources of M3 transistors would be detrimental to the DM tuning range. While obviously the DM oscillation would still work – M3 transistors are off in this mode – the extra capacitance Cfix due to the CM circuitry seen by Cp would be larger. With M8 off, DA/DB node sees Cfix = C1C2/(C1 + C2), but when M3 sources are shorted, that capacitance raises to Cfix = C1 > C1C2/(C1 + C2). Furthermore, an attempt of moving Ms from the SA/SB source nodes of M3 to the DA/DB drain nodes would likewise increase the effective parasitic capacitance of M8. Figure Dual core oscillator waveforms: (a,b) DM and (c,d) CM. The C1 and C2 capacitors are necessary to create a negative resistance for the Colpitts oscillators; however, they are limiting the tuning range in both modes. In their presence, (7.8) and (7.9) are not valid anymore for the overlap and octave tuning. Assuming the same capacitance variation range on the primary and secondary sides, Cp,max/Cp,min = Cs,max/Cs,min, the octave tuning requirement is now where CC = C1C2/(C1 + C2). The minimum overlap condition, fDM,max = fCM,min, dictates Figure 7.11(b) shows how the required Cmax/Cmin increases with CC/Cp ratio. Satisfying (7.11) and (7.10) in the presence of CC also unbalances the DM and CM tuning range, as shown in Figure 7.11(c). For a certain value of CC, the required Cp,max/Cp,min ratio can become prohibitively large, likely leading to the Q-factor degradation. In practice, Cs,max/Cs,min and Cp,max/Cp,min should not be necessarily equal. The secondary-winding capacitor ratio in this design is chosen to be larger than at the primary side due to the tougher Coplitts oscillator start-up conditions.

Ideally, a wide TR oscillator would have a comparable PN performance in both oscillation modes. In this section, we investigate the PN of the dual core oscillator and then compare the two modes. The linear time-variant model [28] suggests where k is Boltzmann’s constant, T is temperature, Rt is the equivalent parallel resistance of the tank, and qmax is the maximum charge displacement across the equivalent capacitance in parallel to Rt. N is the number of resonators, which is 2 here in both DM and CM oscillators. F, the oscillator’s effective noise factor, is in which Γi is the ISF of the ith noise source. The relevant ISF of noise sources associated with a sinusoidal waveform oscillator can be estimated by a π/2 phase shifted sinusoidal function, , where ϕ = ω0t [27]. Here, we try to find the noise factors of different noise sources in the dual core oscillator. The noise sources of the Colpitts oscillator are Rt, M3, and M4. Rt in the CM oscillation is the parallel resistance of the primary winding, Rp. It is insightful to refer every noise source and nonlinearity back to the tank, as it is demonstrated step-by-step in Figure 7.13. The negative conductance between DA and SA nodes is where id3 is the small-signal drain current of M3. The equivalent negative conductance in parallel with the tank is found as With a similar derivation, M3 channel resistance is referred to the tank as To sustain the oscillation, the average dissipated power in the tank loss and Rds3 should be equal to the average power delivered by the negative resistance, which leads to the condition: where n = C1/(C1 + C2), GmEF = Gm[0] − Gm[2], and GdsEF = Gds[0] − Gds[2], in which Gm[k] and Gds[k] are the kth Fourier coefficients of gm(t) and gds(t), respectively [29]. The required GmEF3 is minimized for n = 0.5, which is chosen in this design to facilitate start-up. Figure Procedures of referring the noise back to the tank from: (a) rds3 and negative conductance; (b) gm of M3; and (c) gm of M4. (d) The equivalent circuit of the Colpitts oscillator. To refer the current noise sources to the tank, they are first converted to their Thevenin voltage source equivalents and then converted back to Norton current source equivalents, as demonstrated in Figure 7.13(b) and (c). The equivalent noise of M3 and M4’s transconductance then becomes Figure Noise sources of the DM oscillator [24]. where γ is the transistor excess noise coefficient. Assuming a sinusoidal oscillation, the tank noise factor is found as M3 and M4 noise factors are found as gds4 noise is very small due to M4 operating in a saturation region and, consequently, is disregarded in our calculations. Since gm4 is fairly constant throughout the period, GmEF4 = gm4. To estimate the contribution of M4 to PN, we can calculate gm4 as where Vth is the transistor’s threshold voltage. Let us assign VDD/2 to the SA (SB) node, and VDA ≈ 2I0Rp(1 − n) [27], Disregarding gds4 noise contribution, By substituting (7.17) in (7.21), with GmEF3 and GdsEF3 numerically obtained from simulations, the total oscillator effective noise factor then will be The circuit-to-phase-noise conversion of the CM oscillator is shown in Figure 7.15(a–d). Figure Circuit-to-phase-noise conversion in CM oscillator. Figure (a) Drain and source voltage waveforms. (b) gm3: theory and simulations. The noise contribution of M3 transistor can be numerically calculated based on design parameters. For M3, Vd(ϕ) = VDD + AC cos(ϕ), Vs(ϕ) ≈ VDD/2 + nAC cos(ϕ) and Vg = Vb2. Figure 7.16 shows the M3 operating regions during one oscillating period. At θ0, Vs gets low enough for M3 to turn on and enter the saturation region. When the drain voltage gets lower, M3 enters the triode region at θ1 and remains there till θ2 = 2π − θ1. M3 finally turns off again at θ3 = 2π − θ0. θ0 and θ1 can be found from boundary conditions as and where V1 = VB2 − VDD/2 − Vth and V2 = VB2 − VDD − Vth. Assuming square law, where is the customary designation of MOS transistor strength. GmEF3 now can be determined by calculating the Fourier coefficients of gm3(ϕ). Solving the lengthy integrations results in GmEF3 in (7.31) can be calculated by substituting θ0 and θ1 from (7.28) and (7.29), together with other design parameters: VDD = 1.1 V, VB2 = 1 V, Vth ≈ 0.37 V. Figure 7.16(b) shows a very good agreement (within 15%) with the simulation results. Major noise sources of the DM oscillator are shown in Figure 7.14. A general result of the effective noise factor, assuming that the MT thermal noise is completely filtered out, is derived in [24] as However, the MT thermal noise is not completely filtered out here. To calculate the MT’s noise contribution, the tail node ISF is obtained through simulations and plotted in Figure 7.17(e). From that Hence, the DM oscillator noise factor is The DM oscillator circuit-to-phase-noise conversion is shown in Figure 7.17(a–d). Substituting (7.27) and (7.34) in (7.12) at the overlap frequency results in Due to its single-ended structure and the CM resonance, the Colpitts oscillator would appear to be more sensitive to supply noise. However, that is not the case. Supply pushing is the parameter that indicates the supply noise effect on the phase noise. Figure 7.19(e,f) demonstrates this parameter for the DM and CM oscillators, which is quite comparable, indicating that the CM oscillation does not result in higher phase noise upconversion sensitivity to the supply noise. To explain that, let us look at the actual mechanism: the oscillation frequency can be modulated by the supply noise by modulating the nonlinear voltage-dependent parasitic capacitors of the core transistors, Cgs. In the Colpitts oscillator, the supply voltage is connected to the core transistors’ drains, which cannot modulate their Cgs directly. Consequently, the oscillation frequency modulation due to the supply noise is considerably reduced. Figure (a–d) Circuit-to-phase-noise conversion in DM oscillator; (e) tail transistor ISF; and (f) PN of CM and DM oscillators at the overlap frequency.

The single-ended nature of the Colpitts oscillator makes its characteristics especially sensitive to single-ended parasitics. A key parasitic that must be properly modeled and accounted for is the metal track inductance, LT, which connects the center tap of the transformer’s primary to the supply’s AC-ground (see Figure 7.9(a)). At the DM excitation, the AC current will not flow into LT; thus, the DM inductance and DM resonant frequency are independent of its value. However, at the CM excitation, the current flowing into LT is twice the current circulating in the inductors. Consequently, the tank inductance Lp in Figure 7.9(a) is re-labeled as Lpd = Lp in DM and Lpc = Lpd + 2LT in CM excitations. The CM oscillation frequency will be reduced to . This implies that LT must be carefully modeled and included in simulations, otherwise the increased overlap between CM and DM oscillations would severely limit the total tuning range. Another important parasitic that is only influential in the CM oscillation is the supply loop resistance between the VDD feed to the center-tap of the primary winding and the sources of M4 transistors (see Figure 7.11), assuming sufficient decoupling capacitance on VDD. This resistance is added directly to the equivalent negative resistance of the Colpitts structure and increases it from −gm3/C1C2ω2 to −gm3/C1C2ω2 + rb. In our design, the average of that negative resistance at 6 GHz with C1 = C2 = 1 pF is about −25 Ω, which means the rb parasitic resistance should be kept much smaller as to not endanger the start-up.

The novel oscillator is prototyped in TSMC 40 nm 1P7M CMOS process with top ultra-thick metal. M1,2 are (60/0.27) μm and M3,4 are (128/0.04) μm low-Vth devices for safe start-up of the Colpitts oscillator. The tank employs a 1.4 nH secondary inductor with Q of 25 at 5 GHz and 0.54-nH primary inductor with Q of 17 at 5 GHz. km,DM = 0.72 and km,CM = 0.29. The transformer size is 250 × 250 μm2 and the primary-to-secondary winding spacing is 5 μm. The chip micrograph and transformer characteristics are shown in Figure 7.18, respectively. The oscillator’s core area is 0.12 mm2, which is similar in size to typical narrow tuning-range oscillators. The tank is shared in the two modes of oscillation and so the output is common; hence, no further multiplexing is necessary. A comparison with other relevant wide tuning-range oscillators is summarized in Table 7.1. This oscillator is smaller by at least a factor of 2. The oscillators are tuned via 4-bit switched MOM capacitor banks at the primary and secondary. According to post-layout circuit-level simulations, the tuning range is 46% in DM and 20% in CM, with a 100 MHz overlap, giving the total TR of 63%. However, measurements show that DM oscillator is tunable between 3.37 and 5.32 GHz (45% TR) and the CM oscillator is tunable between 5.02 and 5.96 GHz (17% TR) and the overlap between the DM and CM oscillations is wider than expected, resulting in a tuning range of 55.5%. Figure Transformer characteristics. Table Performance summary and comparison with relevant oscillators Figure 7.19 shows PN at fmax and fmin frequencies of the DM and CM oscillations. In both modes, VDD is 1.1 V. Figure 7.19 also reports the PN and FoM of this oscillator over the tuning range. The FoM increases from 188.2 to 189.4 dB in the DM and from 181.3 to 182.3 dB in the CM tuning ranges. The PN in the CM mode is worse than that in the DM mode, but it is worth mentioning that not all applications demand ultra-low phase noise in all bands and channels uniformly. Table 7.1 also compares FoMA, introduced in [31], of this oscillator with other relevant oscillators. The DM oscillator shows the best FoMA and the CM oscillator’s FoMA is comparable with the other state-of-the-art oscillators.

The measurement results deviate from the simulations and theory in two ways. The first is the wider overlap between the DM and CM oscillation frequencies. The second is the degraded PN in the CM Colpitts oscillator. To explain the performance degradation, we first take a closer look at a layout of the transformer-based tank. As revealed in Figure 7.20, the CM inductance should also include the impedance of the current return route, from the center-tap of the primary winding to the sources of M4a (M4b). The de-coupling capacitors together with the RLC routing network present an equivalent impedance that is inductive but its real part adds to the circuit losses. Therefore, unless the return current path happens to resonate at the same oscillation frequency (through the equivalent inductances and decoupling capacitors along it), the CM oscillation shifts down from the expected value, which is precisely what we observe in our measurements. The DM oscillation frequency is not affected; therefore, the expected TR is decreased. Furthermore, the losses in the return path are added to the losses of the primary inductor, thus degrading the quality factor of the tank. The long return path causes the losses to be comparable to the inductor’s loss and this jeopardizes the CM start-up. Furthermore, this path also partially cancels the magnetic field of the inductor, thus degrading its Q-factor. The severe PN degradation compared to the simulation results gives, thus, credence to the Q degradation of the tank. Our EM simulations predict a 0.25-Ω resistance in this path and circuit simulations show that such resistance in series with the primary inductor would degrade the CM oscillator phase noise by 4 dB. This appears to agree with our measurements. Figure (a) Measured PN at fDM,max, fDM,min; (b) fCM,max and fCM,min. Measured (c) PN and (d) FoM at 10-MHz offset across TR. Frequency pushing due to supply voltage variation in (e) DM and (f) CM oscillators. Figure Return current path in the 1:2 transformer. One possible solution would be employing a 2:1 transformer. A 2-turn primary inductor will have its supply connection node very close to the transistors; therefore, the current return path would not be very long, thus minimizing the path inductance. However, in that transformer, the CM current in the two windings of the primary inductor has opposite direction, thus canceling each other’s flux [30]. Consequently, the CM primary inductance would be smaller than the DM one. The spacing between the transformer windings should be chosen properly to satisfy the overlap condition for the reasonable capacitor bank Con/Coff ratios.

In this chapter, we have introduced a technique to extend a tuning range (TR) of an LC-tank oscillator without significantly increasing its die area. A strongly coupled 1:2 turns-ratio transformer-based tank is normally excited in a differential mode (DM), where it achieves the TR of 45% with a good FoM of 188.2–189.4 dB. The TR is extended by exciting the tank in common mode (CM) with two locked Colpitts oscillators. This oscillator is implemented in 40 nm CMOS and delivers the total TR of 55.5% while constraining the core die area to only 0.12 mm2. Although the measured tuning range extension and phase noise (PN) in the CM mode were worse than theoretically predicted, we have identified the common cause as a current return route inductance that not only lowers the CM frequencies but also adds losses that result in a reduced Q-factor.

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In this chapter, we investigate the nature of oxide breakdown and stress-related degradation mechanisms in MOS transistors. The MOS breakdown time is quantified based on exponential-law and defect-generation models versus the oxide-thickness, gate area, temperature, and voltage stress at a given cumulative failure. As a consequence, a design guide is presented to estimate the time-dependent dielectric breakdown of any analog circuit. Based on reliability analysis, the lifetime of class-F3 oscillator of Chapter 3 is evaluated for both thin- and thick-oxide options in TSMC 65-nm CMOS process as a case study. The long-term reliability is also investigated for class-F2 oscillator introduced in Chapter 4.

To keep on implementing increasingly complex functions while reducing the overall solution costs, scaling of CMOS transistors is inevitable. As circuits are growing denser, all of the physical dimensions of the transistors must be reduced correspondingly. The SiO2 oxide-layer thickness reduction is accompanied by migrating to smaller supply voltages. This is to maintain the electric field strength across the oxide in order to prevent the device performance degradation due to the time-dependent dielectric breakdown (TDDB) [1]. Although digital circuits have fared well, analog designers face additional difficulties with the transistor scaling. The supply voltage VDD is reduced while RF and analog circuits must maintain their dynamic range, noise performance, and output power. For example, the oscillator phase noise performance and power amplifier (PA) output power degrade by 6 dB/octave with reduction of their supply voltage [2, 3]. On the other hand, LC-tank oscillators and PAs usually operate at a voltage swing in excess of the nominal supply voltage. This causes potential reliability issues due to the large electric field across the gate oxide. Consequently, analog designers must consider the reliability of the circuit while trying to maximize the voltage swing to reach better output power, dynamic range, or noise performance. In the classical view, the reliability must be qualified at the technology level and guaranteed by the manufacturer. However, this perception is no longer valid. The circuit reliability has become highly circuit-dependent in the advanced CMOS technologies. The designers have to improve the reliability margins by adapting their approach and taking into account the impact of failure at the circuit level. In this chapter, we investigate the nature of oxide breakdown and stress-related degradation mechanisms in MOS transistors. The maximum gate-oxide voltage of a MOS transistor is quantified versus the oxide thickness, gate area, and temperature for different cumulative failure rates and operating times. We exemplify the oxide breakdown reliability calculations in class-F RF oscillators of Chapters 3 and 4.

Gate-oxide breakdown leads to a catastrophic and permanent failure in MOS devices. The breakdown is accompanied by a sudden discontinuous increase in the oxide conductance and the gate current noise. Breakdown is a gradually increasing phenomenon and realized by defects such as electron traps in the oxide structure. The rate of defect generation is almost proportional to the gate current density. As a consequence, the transistors with a smaller channel length are more vulnerable. The gate current is due to Fowler–Nordheim (FN) tunneling for thick-oxide devices at a gate voltage Vg above 3 V, while it is due to a direct quantum-mechanical tunneling (DT) for thin oxides (tox ≤ 3-nm) at voltages below 3 V [4]. These gate currents trigger “impact ionization”, “anode hole injection”, and “trap creation” phenomena to generate defects in the oxide structure. Then, the probable breakdown will occur at a critical trap density by a conduction path via these generated traps. Consequently, the oxide breakdown failure is a time-dependent and statistically distributed phenomenon. It is well known that the oxide breakdown can be described by the Weibull distribution [1]: where F is a cumulative failure probability and TBD is a random variable for time-to-breakdown. η is a characteristic time-to-breakdown at 63.2% failure probability and β is a Weibull shape slope. Figure Weibull slope versus gate-oxide thickness.

Figure 8.1 shows measured Weibull slopes obtained from literature [5] versus oxide thickness ranging from 1.25 to 7 nm at a temperature of 140°C. The solid curve is a linear fit of an analytical cell-based model and expressed by where α0 is the defect size that is found to be 1.83 nm in [5] and tint is the interface thickness, which was reported 0.37 nm in [5]. Equation (8.2) indicates that Weibull slope decreases with the technology scaling. Suppose the η value is the same for both thin- and thick-oxide devices. Although both devices reach the cumulative failure rate of 63% at the same time, the early failure rate of a thin-oxide transistor will be much larger than that of the thick-oxide device due to its lower Weibull slope. Consequently, thin-oxide devices can only tolerate lower electric field strengths for the certain failure rate in a given operating time. It is concluded in [1] that Weibull slope is independent over a wide range of stress voltage, temperature, and polarity.

Figure 8.2 shows η versus gate voltage for different oxide thicknesses. The data points (open/solid squares, triangles, and circles) are extracted from literature [1, 4, 9] and scaled to 140°C and an area of 103 μm2. The TDDB reliability is usually estimated by means of voltage and temperature acceleration models from results acquired at relatively short measurement times to the required product lifetime of 10 years or more. Such a scaling may span several decades and magnify inaccuracies if the model is not correct or the breakdown mechanism changes along the voltage scaling. Until now, at least five voltage acceleration models have been proposed: E-model, 1/E model, power-law model, 1/V model, and physics-based model. Not surprisingly, it is confusing and practically impossible to decide which model should be used in TDDB calculations. Figure Comparison of characteristic time-to-breakdown η versus gate voltage in NMOS inversion for different gate-oxide thicknesses from 1.5 to 12 nm. The solid lines represent the result of defect generation model as described in [7]. The dashed lines are from the least-square fit using the E-model, as described in [9]. The data points (open/solid squares, triangles, and circles) are extracted from literature and scaled to 140°C with an area of 103 μm2. The field-driven E-model refers to the experimental observation that TBD data can be characterized by exp(γ · Eox), where the electric field Eox is considered as a variable in TDDB process [9]. The η variations based on E-model curve fitting are illustrated by dashed lines in Figure 8.2 for different oxide thicknesses. The model can be safely ruled out for both thin and thick oxide at Eox ≥ 7 MV/cm. However, an extrapolation to lower fields would result in a cross-over between the dashed lines meaning thick-oxide devices are less reliable than thin-oxide ones at voltages below 1.5 V, which is contradictory to the fundamental physics. Consequently, this model is not accurate at Eox ≤ 7 MV/cm. Nevertheless, it is possible to use E-model as a conservative projection. Hence, E-model estimation has been added in Figure 8.2 as the worst case in TBD prediction [7]. The anode injection model (1/E model) characterizes TBD based on the FN tunneling current. However, the direct tunneling is a dominant phenomenon at Vg ≤ 4 V. Hence, 1/E model is not applicable and leads to optimistic results at lower voltages [8]. A more realistic projection is the physics-based breakdown model, which considers both tunneling current and defect generation phenomena. This model is consistent with many measurement results up to the 8-nm oxide thickness. The discrepancy at thicker oxides originates in “band-to-band ionization”, which plays an important role in very thick oxides stressed at relatively high voltages [7]. The η extrapolation based on “defect-generation” model is also added by solid lines in Figure 8.2 for different oxide thicknesses.

The failure of an entire IC chip is defined by the first failure of a single device. From elementary statistics, if the failure probability of a unit is FA1, then the failure probability of a circuit comprising N independent units is given by By substituting (8.1) into (8.3) and carrying out lengthy algebra, the area scaling equation of η is obtained by where A1 and A2 correspond to two different areas of the oxide. This expression shows that the characteristic breakdown time, η, increases with reducing the oxide area. The area scaling is a strong function of the Weibull slope and, consequently, thinner oxides are more sensitive. For example, in 10−4 to 10 mm2 area scaling, TBD lifetime drops with 3–4 orders of magnitude for a 4-nm oxide. However, the TBD reduction would be just a factor of 2 for an 11-nm oxide. The following equation expresses the dependency of η on the oxide junction temperature [6]. As expected, higher temperatures accelerate the TDDB process. where KB is the Boltzmann’s constant and Ea is the thermal activation energy that is about 1 eV and changes by a small amount with the gate voltage [6].

Figure 8.2 shows the extrapolated η for physics-based and E models for an area 103 μm2 at 140°C. The main question arises: How can one predict TDDB lifetime of a circuit for a given voltage and cumulative failure values based on this figure? The principle of TBD extrapolation to a specified condition is illustrated in Figure 8.3. As a first step, one of the curves in Figure 8.2 is chosen based on the technology oxide thickness. This curve will shift through (8.5) if the operating temperature deviates from the reference value 140°C. Then, the area scaling is applied to the graph using (8.4). The curve is scaled once more to the desired cumulative failure by (8.1). Finally, the corresponding TBD can be calculated from the obtained curve (blue dashed-line in Figure 8.3) for any gate voltages. Figure Extrapolation steps to the specified condition.

Hot carriers (HC) are holes or electrons that are accelerated to high energies by an electric field caused by a large drain–source voltage. Certain percentage of the hot carriers collide with the lattice and create electron–hole pairs. Furthermore, if the hot charge carriers have a kinetic energy larger than the silicon-oxide barrier height, some of them will dominate the barrier and flow toward the insulator. Unlike the gate-oxide breakdown, this phenomenon is not inherently catastrophic. Instead, it can cause a gradual performance degradation during the operating lifetime. These traps can shift the threshold voltage and reduce the conducting carrier mobility. Consequently, the drain current, channel resistance, and transconductance gain of MOS transistor decrease and degrade performance of RF circuits, such as oscillators. First, one needs to choose larger gm-devices to compensate the oscillator loop gain reduction due to HC. It means the active device injects more noise into the tank, resulting in an increase of the oscillator’s effective noise factor. Furthermore, the circuit phase noise performance gradually degrades due to reduction of drain current and thus the oscillation voltage swing. Hence, an additional mechanism should sense the oscillation amplitude in order to increase the drain current of active devices by adjusting their bias voltage. Second, a combination of a large parasitic capacitance of the tail current transistor and a smaller channel resistance of the gm-device could provide a discharge path between the tank and ground. It would drop the equivalent quality factor of the tank resulting in phase noise degradation. Third, hot carrier stress also increases the 1/f noise of the MOS transistor, which is translated to a larger 1/f3 oscillator phase noise corner. However, the hot carrier degradation mainly occurs when the drain current and drain–source voltage are substantial at the same time [3]. Hence, the hot carrier degradation would be negligible if the channel current was low when the drain–source voltage was high and vice versa. This condition naturally occurs in oscillators and switching power amplifiers. Consequently, the RF oscillators are not inherently vulnerable to the hot carrier degradation.

The negative bias temperature instability (NBTI) occurs when a negative gate–source voltage Vgs is applied causing an increase in the absolute threshold voltage, a degradation of the mobility, drain current, and transcon-ductance. PMOS devices are more vulnerable to NBTI. Although NMOS devices can be damaged in an NBTI stress, the damage occurs at negative Vgs where NMOS devices are not active. Consequently, NMOS devices are thus suggested for long operating time applications such as infrastructure basestations and satellite communications.

Figure 8.4(a) shows a schematic of the class-F3 oscillator in Chapter 3, which was realized in TSMC 65-nm CMOS technology. It exhibits a pseudo-square-wave across the tank to desensitize the oscillator phase noise to the circuit noise. Figure 8.4(b) illustrates the oscillation waveforms. As can be seen, gate–drain voltage increases to 3.2 V at 1.2-V supply voltage due to the passive voltage gain of the transformer. M1/2 dimensions should be (48-μm/0.28-μm) and (12-μm/65-nm) for thick (5 nm) and thin (2.3 nm) oxide options, respectively, to guarantee safe oscillator start-up in all process corners. Let us investigate the oscillator’s lifetime at 0.01% cumulative failure rate and 140°C for both transistors. From Figure 8.5, the η values are obtained as Figure Class-F oscillator: (a) schematic; (b) waveforms. The conservative E-model is used for the TBD calculations. Weibull slope should be determined in order to extrapolate η values to the desired area. Based on (8.2), Figure Class-F3 oscillator lifetime estimation due to TDDB for thin- and thick-oxide transistors. The next step is to apply the area scaling factor to η by (8.4). Finally, the lifetime can be estimated by substituting the calculated parameters in (8.4): The oscillator lifetime drops dramatically by 4 orders of magnitude just by replacing thick-oxide gm-devices with thin-oxide ones. Consequently, a thick-oxide device must be used in the class-F3 oscillator to satisfy the required TBD and failure rate but at a cost of more parasitic capacitance and lower tuning range.

The HCI degradation would occur when the drain current, Ids, and drain-source voltage, VDS, are large at the same time. Thanks to the transformer’s voltage gain, in class-F2 oscillator, VDD is low enough such that VDS of its gm-devices can be much less than the standard voltage of thick-oxide transistors (2.5 V) when they operate in on-state (see Figure 4.11). Consequently, this oscillator is not inherently vulnerable to HCI. However, the large oscillation swing applies a strong electric field across the gate oxide of gm-devices (VDG, VGS), which can potentially reduce the long-term reliability of the oscillator due to TDDB. The oxide breakdown stems from defects, such as electron traps, in the oxide structure. The rate of defect generation is almost proportional to the gate-oxide electric field and its leakage current density. We can re-write Equation (8.1) as It is shown in [1] that η for a given circuit with arbitrary characteristics (Aox, Vox, and Tox) can be extrapolated from the reference data (xref) by where n is voltage acceleration factor. We can apply the above procedure to our class-F2 oscillator to determine its Tbd. Figure 8.6(a) shows the measured F versus TBD for 14 samples of the thick-oxide transistor (176 μm/0.28 μm) at room temperature when a large voltage (6.75 and 7 V) is applied across the gate. The data points are easily mapped to a Weibull distribution curve as indicated by the dashed line. The cross-over of these curves at F = 63.2% specifies the reference η values (ηref). The voltage acceleration ratio n is calculated by applying ηref values and their related Vox in (8.11). Furthermore, the slope of the curves determines β. Consequently, the estimated n and β values are, respectively, 42 and 3 for the thick-oxide devices (tox = 5.6 nm) in 65-nm CMOS, which are close to extracted measured numbers from literature, as shown in Figure 8.6(c,d) [1,10]. The Ea is ∼0.55 eV and independent from the oxide thickness and temperature [11]. Consequently, the given oscillator η can be estimated by substituting the measured reference and technology parameters and circuit characteristics (Aox, Vox, and Tox) in (8.11). Finally, TBD is calculated by substituting the estimated η and the desired F in (8.10). Figure (a) Measured cumulative failure rate F versus breakdown time TBD for 14 samples of a thick-oxide transistor (176 μm/0.28 μm) at room temperature, (b) the projected η value versus different gate-oxide stress voltage based on the measured ηref, (c) Weibull slope versus gate-oxide thickness extracted from measurement results in [1], and (d) voltage acceleration versus gate-oxide thickness extracted from measurement results in [10]. The lifetime estimation of our circuit as a function of Vox is plotted in Figure 8.7 for various F, Tox, and Aox. The plots indicate that the maximum voltage across the oxide for M1,2 transistors should be <4.4 V to ensure <0.01% failure during 10 years at 125°C. The max Vox could be increased if higher failure rate or lower max operating temperature are accepted. The maximum dc voltage is thus established across the gate oxide. However, the actual nature of stress in RF oscillators is not dc but an ac voltage Vox(ω0t). Consequently, it is instructive to compare the static max Vox with the actual operation when η changes over the period of the resonant frequency. Hence, the “effective” η is calculated as where η(Vox(ω0t)) is given by (8.11) and can be expediently simplified to η = B · (Vox(ω0t))−n. Figure Estimated time-to-breakdown (based on the measured parameters of Figure 8.6(a)) of thick-oxide transistors in 65-nm CMOS versus maximum gate-oxide stress voltage for different (a) cumulative failure rates, (b) temperatures, and (c) gate-oxide areas. Starting with the application’s desired operating time (i.e., TBD) at a given failure rate (F) in a given technology (i.e., β), the parameter ηeff is first established as per (8.10) and is identical for dc and ac operations. For a dc operation, η = B · (Vdc)−n and (8.12) results in However, for an ac operation, Solving this integral for the voltage acceleration factor n of 42 for the 65-nm CMOS thick-oxide devices, Consequently, the ac to dc maximum tolerable stress voltage ratio (Vac,max/Vdc) will be (11.5)1/n ≈ 1.06. We strongly emphasize that there are no significant differences in max Vox at ac-peak and dc conditions due to the sharp slope of TBD − Vox curves in Figure 8.7. As shown by integrating the voltage-dependent η(Vox) over the full oscillation cycle, the peak magnitude of the Vox sine wave can be just 6% higher than what is determined for a fixed dc Vox. Consequently, the slightly lower pessimistic value of Vox in the dc condition could be used as an extra margin.

Time-dependent dielectric breakdown (TDDB), hot carrier degradation (HCI), and negative bias temperature instability (NBTI) mechanisms were investigated for a MOS transistor. The exponential-law and defect-generation models quantified the MOS breakdown lifetime versus the oxide-thickness, gate area, temperature, gate voltage, and cumulative failure rate. A design guide is presented to estimate TDDB of any analog circuit. Based on reliability analysis, a huge 4-decade lifetime difference exists between thin (2.3-nm) and thick (5-nm) oxide devices in the class-F3 oscillator. The reliability process is highly circuit-dependent in the advanced CMOS technologies (oxide thickness ≤ 3 nm) and analog/RF engineers have to consider the reliability issues in the design cycle.

[1] E. Y. Wu, et al., “CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics,” IBM Journal of Research and Development, vol. 46, no. 2/3, pp. 287–297, Mar./May 2002. [2] M. Babaie and R. B. Staszewski, “Third-harmonic injection technique applied to a 5.87- to 7.56 GHz 65nm class-F oscillator with 192dBc/Hz FoM,” Proc. of IEEE Solid-State Circuits Conf., pp. 348–349, Feb. 2013. [3] I. Aoki, et al., “A fully integrated quad-band GSM/GPRS CMOS power amplifier,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2747–2758, Dec. 2008. [4] J. H. Stathis, “Physical and predictive models of ultrathin oxide reliability in CMOS devices and circuits,” IEEE Transactions on Device and Materials Reliability, vol. 1, no. 1, pp. 43–59, Mar. 2001. [5] E. Y. Wu, J. Sune, and W. Lai, “On the Weibull Shape Factor of Intrinsic Breakdown of Dielectric Films and Its Accurate Experimental Determination – Part II: Experimental Results and the Effects of Stress Conditions,” IEEE Transactions on Electron Devices, vol. 49, no. 12, pp. 2141–2150, Dec. 2002. [6] A. M. Yassine, et al., “Time dependent breakdown of ultrathin gate oxide” IEEE Transactions on Electron Devices, vol. 47, no. 7, pp. 1416– 1420, Jul. 2000. [7] E. Y. Wu, et al., “Comprehensive physics-based breakdown model for reliability assessment of oxides with thickness ranging from 1 nm up to 12 nm,” Proceedings of the 47th Annual International Reliability Physics Symposium (IRPS), pp. 708–717, Montreal 2009. [8] I. C. Chen, et al., “Electrical breakdown in thin gate and tunneling oxides,” IEEE Journal of Solid-State Circuits, vol. 20, no. 1, pp. 333–342, Feb. 1985. [9] A. Berman, “Time-zero dielectric reliability test by a ramp method,” in IEEE Proc. International Reliability Physics Symp., 1981, pp. 204–209. [10] E. Wu, J. Aitken, E. Nowak, A. Vayshenker, P. Varekamp, G. Hueckel, J. McKenna, D. Harmon, L. K. Han, C. Montrose, and R. Dufresne, “Voltage-dependent voltage acceleration of oxide breakdown for ultra-thin oxides,” IEEE International Electron Devices Meeting (IEDM), 2000, pp. 541–544. [11] E. Wu, J. McKenna, W. Lai, E. Nowak, and A. Vayshenker, “The effect of change of voltage acceleration on temperature activation of oxide breakdown for ultrathin oxides,” IEEE Electron Device Letters, vol. 22, no. 12, pp. 603–605, Dec. 2001.

Masoud Babaie received the B.Sc. degree (Hons.) in electrical engineering from the Amirkabir University of Technology, Tehran, Iran, the M.Sc. degree in electrical engineering from the Sharif University of Technology, Tehran, and the Ph.D. degree (cum laude) in electrical engineering from the Delft University of Technology, Delft, The Netherlands, in 2004, 2006, and 2016, respectively. In 2006, he joined the Kavoshcom Research and Development Group, Tehran, where he was involved in designing wireless communication systems. From 2009 to 2011, he was a CTO of that company. He was consulting for RF group of TSMC, Hsinchu, Taiwan, in 2013–2015, designing 28-nm All-Digital PLL and Bluetooth Low Energy transceiver chips. From 2014 to 2015, he was a Visiting Scholar Researcher with the Berkeley Wireless Research Center, Berkeley, CA, USA. In 2016, he joined the Delft University of Technology, Delft, The Netherlands, as an Assistant Professor. His current research interests include RF/millimeter-wave integrated circuits and systems for wireless communications, and cryogenic electronics for quantum computation. Dr. Babaie has been a Committee Member of Student Research Preview (SRP) of the IEEE International Solid-State Circuits Conference (ISSCC), since 2017. He was a recipient of the 2015–2016 IEEE Solid-State Circuits Society Pre-Doctoral Achievement Award. In 2019, he received the Veni award from The Netherlands Organization for Scientific Research (NWO). Mina Shahmohammadi received the B.Sc. degree in communication systems from the Amirkabir University of Technology, Tehran, Iran, in 2005, the M.Sc. degree in electronics from the University of Tehran, Tehran, in 2007, and the Ph.D. degree from Electronics Research Laboratory, Delft University of Technology (TU Delft), Delft, The Netherlands, in 2016, with a focus on wide tuning range and low flicker noise RF-CMOS oscillators. From 2007 to 2011, she was with Rezvan Engineering Company, Tehran, as an Analog Designer. She was a Research Assistant with the Electronic Instrumentation Laboratory, TU Delft, from 2011 to 2013, where she was involved in resistor-based temperature sensors. She is currently an Analog Designer with Catena B.V., Delft. Her current research interests include analog and RF integrated circuits design. Robert Bogdan Staszewski was born in Bialystok, Poland. He received the B.Sc. (summa cum laude), M.Sc., and Ph.D. degrees in electrical engineering from the University of Texas at Dallas, Richardson, TX, USA, in 1991, 1992, and 2002, respectively. From 1991 to 1995, he was with Alcatel Network Systems in Richardson, TX, USA, involved in SONET cross-connect systems for fiber optics communications. He joined Texas Instruments Incorporated, Dallas, TX, USA, in 1995 where he was elected Distinguished Member of Technical Staff (limited to 2% of technical staff). From 1995 to 1999, he was engaged in advanced CMOS read channel development for hard disk drives. In 1999, he co-started the Digital RF Processor (DRP) group within Texas Instruments with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deeply-scaled CMOS technology. He was appointed as a CTO of the DRP group from 2007 to 2009. In 2009, he joined the Delft University of Technology, Delft, The Netherlands, where currently he holds a guest appointment of Full Professor (Antoni van Leeuwenhoek Hoogleraar). Since 2014, he has been a Full Professor with the University College Dublin (UCD), Dublin, Ireland. He has authored or co-authored four books, five book chapters, 260 journal and conference publications, and holds 180 issued US patents. His research interests include nanoscale CMOS architectures and circuits for frequency synthesizers, transmitters and receivers. Prof. Staszewski has been a TPC member of ISSCC, RFIC, ESSCIRC, ISCAS and RFIT. He is an upcoming TPC Chair of 2019 ESSCIRC in Krakow, Poland. He was a recipient of the 2012 IEEE Circuits and Systems Industrial Pioneer Award.